forked from OSchip/llvm-project
[ARM] add overrides for isCheapToSpeculateCttz() and isCheapToSpeculateCtlz()
ARM V6T2 has instructions for efficient count-leading/trailing-zeros, so this should be considered a cheap operation (and therefore fair game for speculation) for any ARM V6T2 implementation. The net result of allowing this speculation for the regression tests in this patch is that we get this code: ctlz: clz r0, r0 bx lr cttz: rbit r0, r0 clz r0, r0 bx lr Instead of: ctlz: cmp r0, #0 moveq r0, #32 clzne r0, r0 bx lr cttz: cmp r0, #0 moveq r0, #32 rbitne r0, r0 clzne r0, r0 bx lr This will help solve a general speculation/despeculation problem noted in PR24818: https://llvm.org/bugs/show_bug.cgi?id=24818 Differential Revision: http://reviews.llvm.org/D14469 llvm-svn: 252639
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parent
8cf44d9684
commit
af1b48bfdc
llvm
lib/Target/ARM
test/Transforms/SimplifyCFG/ARM
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@ -11841,6 +11841,14 @@ bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
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return false;
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}
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bool ARMTargetLowering::isCheapToSpeculateCttz() const {
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return Subtarget->hasV6T2Ops();
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}
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bool ARMTargetLowering::isCheapToSpeculateCtlz() const {
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return Subtarget->hasV6T2Ops();
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}
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Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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AtomicOrdering Ord) const {
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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@ -467,6 +467,9 @@ namespace llvm {
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bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
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unsigned &Cost) const override;
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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protected:
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std::pair<const TargetRegisterClass *, uint8_t>
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findRepresentativeClass(const TargetRegisterInfo *TRI,
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@ -0,0 +1,43 @@
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; RUN: opt -S -simplifycfg -mtriple=arm -mattr=+v6t2 < %s | FileCheck %s
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define i32 @ctlz(i32 %A) {
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; CHECK-LABEL: @ctlz(
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; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
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; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
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; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
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; CHECK-NEXT: ret i32 [[SEL]]
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entry:
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%tobool = icmp eq i32 %A, 0
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br i1 %tobool, label %cond.end, label %cond.true
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cond.true:
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%0 = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
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ret i32 %cond
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}
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define i32 @cttz(i32 %A) {
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; CHECK-LABEL: @cttz(
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; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
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; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
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; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
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; CHECK-NEXT: ret i32 [[SEL]]
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entry:
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%tobool = icmp eq i32 %A, 0
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br i1 %tobool, label %cond.end, label %cond.true
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cond.true:
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%0 = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
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br label %cond.end
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cond.end:
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%cond = phi i32 [ %0, %cond.true ], [ 32, %entry ]
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ret i32 %cond
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}
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declare i32 @llvm.ctlz.i32(i32, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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@ -0,0 +1,5 @@
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config.suffixes = ['.ll']
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targets = set(config.root.targets_to_build.split())
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if not 'ARM' in targets:
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config.unsupported = True
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