forked from OSchip/llvm-project
[Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ
llvm-svn: 333760
This commit is contained in:
Krzysztof Parzyszek
parent
6eb680a40d
commit
aec2c0c9b6
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@ -425,6 +425,7 @@ namespace HexagonISD {
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SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
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@ -69,21 +69,25 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal);
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setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal);
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setOperationAction(ISD::AND, ByteV, Legal);
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setOperationAction(ISD::OR, ByteV, Legal);
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setOperationAction(ISD::XOR, ByteV, Legal);
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for (MVT T : LegalV) {
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setIndexedLoadAction(ISD::POST_INC, T, Legal);
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setIndexedStoreAction(ISD::POST_INC, T, Legal);
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setOperationAction(ISD::ADD, T, Legal);
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setOperationAction(ISD::SUB, T, Legal);
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setOperationAction(ISD::AND, T, Legal);
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setOperationAction(ISD::OR, T, Legal);
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setOperationAction(ISD::XOR, T, Legal);
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setOperationAction(ISD::ADD, T, Legal);
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setOperationAction(ISD::SUB, T, Legal);
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setOperationAction(ISD::CTPOP, T, Legal);
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setOperationAction(ISD::CTLZ, T, Legal);
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if (T != ByteV) {
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setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
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setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
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setOperationAction(ISD::BSWAP, T, Legal);
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}
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setOperationAction(ISD::CTTZ, T, Custom);
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setOperationAction(ISD::LOAD, T, Custom);
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setOperationAction(ISD::MUL, T, Custom);
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setOperationAction(ISD::MULHS, T, Custom);
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@ -104,6 +108,9 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::SRA, T, Custom);
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setOperationAction(ISD::SHL, T, Custom);
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setOperationAction(ISD::SRL, T, Custom);
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// Promote all shuffles to operate on vectors of bytes.
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setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV);
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}
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setCondCodeAction(ISD::SETNE, T, Expand);
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@ -115,16 +122,6 @@ HexagonTargetLowering::initializeHVXLowering() {
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setCondCodeAction(ISD::SETULT, T, Expand);
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}
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for (MVT T : LegalV) {
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if (T == ByteV)
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continue;
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// Promote all shuffles to operate on vectors of bytes.
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setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV);
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setPromoteTo(ISD::AND, T, ByteV);
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setPromoteTo(ISD::OR, T, ByteV);
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setPromoteTo(ISD::XOR, T, ByteV);
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}
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for (MVT T : LegalW) {
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// Custom-lower BUILD_VECTOR for vector pairs. The standard (target-
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// independent) handling of it would convert it to a load, which is
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@ -145,6 +142,9 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::LOAD, T, Custom);
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setOperationAction(ISD::STORE, T, Custom);
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setOperationAction(ISD::CTLZ, T, Custom);
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setOperationAction(ISD::CTTZ, T, Custom);
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setOperationAction(ISD::CTPOP, T, Custom);
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setOperationAction(ISD::ADD, T, Legal);
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setOperationAction(ISD::SUB, T, Legal);
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@ -1157,6 +1157,40 @@ HexagonTargetLowering::LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const {
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return Op;
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}
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SDValue
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HexagonTargetLowering::LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const {
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// Lower vector CTTZ into a computation using CTLZ (Hacker's Delight):
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// cttz(x) = bitwidth(x) - ctlz(~x & (x-1))
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const SDLoc &dl(Op);
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MVT ResTy = ty(Op);
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SDValue InpV = Op.getOperand(0);
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assert(ResTy == ty(InpV));
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// Calculate the vectors of 1 and bitwidth(x).
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MVT ElemTy = ty(InpV).getVectorElementType();
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unsigned ElemWidth = ElemTy.getSizeInBits();
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uint32_t Splat1 = 0, SplatW = 0;
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assert(isPowerOf2_32(ElemWidth) && ElemWidth <= 32);
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for (unsigned i = 0; i != 32/ElemWidth; ++i) {
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Splat1 = (Splat1 << ElemWidth) | 1;
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SplatW = (SplatW << ElemWidth) | ElemWidth;
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}
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SDValue Vec1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy,
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DAG.getConstant(Splat1, dl, MVT::i32));
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SDValue VecW = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy,
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DAG.getConstant(SplatW, dl, MVT::i32));
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SDValue VecN1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy,
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DAG.getConstant(-1, dl, MVT::i32));
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// Do not use DAG.getNOT, because that would create BUILD_VECTOR with
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// a BITCAST. Here we can skip the BITCAST (so we don't have to handle
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// it separately in custom combine or selection).
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SDValue A = DAG.getNode(ISD::AND, dl, ResTy,
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{DAG.getNode(ISD::XOR, dl, ResTy, {InpV, VecN1}),
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DAG.getNode(ISD::SUB, dl, ResTy, {InpV, Vec1})});
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return DAG.getNode(ISD::SUB, dl, ResTy,
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{VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)});
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}
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SDValue
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HexagonTargetLowering::LowerHvxMul(SDValue Op, SelectionDAG &DAG) const {
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MVT ResTy = ty(Op);
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@ -1422,6 +1456,8 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::LOAD:
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case ISD::STORE:
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return SplitHvxMemOp(Op, DAG);
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case ISD::CTLZ:
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case ISD::CTTZ:
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case ISD::MUL:
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case ISD::MULHS:
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case ISD::MULHU:
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@ -1451,6 +1487,7 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG);
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case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG);
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case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG);
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case ISD::CTTZ: return LowerHvxCttz(Op, DAG);
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case ISD::SRA:
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case ISD::SHL:
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case ISD::SRL: return LowerHvxShift(Op, DAG);
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@ -250,7 +250,19 @@ let Predicates = [UseHVX] in {
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def: Pat<(VecPI32 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>;
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}
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class Vneg1<ValueType VecTy>
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: PatFrag<(ops), (VecTy (HexagonVSPLATW (i32 -1)))>;
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class Vnot<ValueType VecTy>
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: PatFrag<(ops node:$Vs), (xor $Vs, Vneg1<VecTy>)>;
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let Predicates = [UseHVX] in {
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let AddedComplexity = 200 in {
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def: Pat<(Vnot<VecI8> HVI8:$Vs), (V6_vnot HvxVR:$Vs)>;
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def: Pat<(Vnot<VecI16> HVI16:$Vs), (V6_vnot HvxVR:$Vs)>;
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def: Pat<(Vnot<VecI32> HVI32:$Vs), (V6_vnot HvxVR:$Vs)>;
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}
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def: OpR_RR_pat<V6_vaddb, Add, VecI8, HVI8>;
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def: OpR_RR_pat<V6_vaddh, Add, VecI16, HVI16>;
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def: OpR_RR_pat<V6_vaddw, Add, VecI32, HVI32>;
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@ -378,6 +390,21 @@ let Predicates = [UseHVX] in {
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(V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
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def: Pat<(VecI32 (bswap HVI32:$Vs)),
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(V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x03030303)))>;
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def: Pat<(VecI8 (ctpop HVI8:$Vs)),
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(V6_vpackeb (V6_vpopcounth (HiVec (V6_vunpackub HvxVR:$Vs))),
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(V6_vpopcounth (LoVec (V6_vunpackub HvxVR:$Vs))))>;
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def: Pat<(VecI16 (ctpop HVI16:$Vs)), (V6_vpopcounth HvxVR:$Vs)>;
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def: Pat<(VecI32 (ctpop HVI32:$Vs)),
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(V6_vaddw (LoVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))),
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(HiVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))))>;
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def: Pat<(VecI8 (ctlz HVI8:$Vs)),
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(V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
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(V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
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(V6_lvsplatw (A2_tfrsi 0x08080808)))>;
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def: Pat<(VecI16 (ctlz HVI16:$Vs)), (V6_vcl0h HvxVR:$Vs)>;
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def: Pat<(VecI32 (ctlz HVI32:$Vs)), (V6_vcl0w HvxVR:$Vs)>;
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}
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class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
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@ -0,0 +1,124 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: f0
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; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vunpack(v0.ub)
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; CHECK-DAG: v[[V02:[0-9]+]].h = vpopcount(v[[V00]].h)
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; CHECK-DAG: v[[V03:[0-9]+]].h = vpopcount(v[[V01]].h)
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; CHECK: v0.b = vpacke(v[[V02]].h,v[[V03]].h)
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define <128 x i8> @f0(<128 x i8> %a0) #0 {
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%t0 = call <128 x i8> @llvm.ctpop.v128i8(<128 x i8> %a0)
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ret <128 x i8> %t0
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}
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; CHECK-LABEL: f1
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; CHECK: v0.h = vpopcount(v0.h)
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define <64 x i16> @f1(<64 x i16> %a0) #0 {
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%t0 = call <64 x i16> @llvm.ctpop.v64i16(<64 x i16> %a0)
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ret <64 x i16> %t0
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}
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; CHECK-LABEL: f2
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; CHECK: v[[V20:[0-9]+]].h = vpopcount(v0.h)
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; CHECK: v[[V21:[0-9]+]]:[[V22:[0-9]+]].uw = vzxt(v[[V20]].uh)
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; CHECK: v0.w = vadd(v[[V22]].w,v[[V21]].w)
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define <32 x i32> @f2(<32 x i32> %a0) #0 {
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%t0 = call <32 x i32> @llvm.ctpop.v32i32(<32 x i32> %a0)
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ret <32 x i32> %t0
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}
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; CHECK-LABEL: f3
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; CHECK-DAG: r[[R30:[0-9]+]] = ##134744072
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; CHECK-DAG: v[[V31:[0-9]+]]:[[V32:[0-9]+]].uh = vunpack(v0.ub)
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; CHECK: v[[V33:[0-9]+]] = vsplat(r[[R30]])
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; CHECK-DAG: v[[V34:[0-9]+]].uh = vcl0(v[[V31]].uh)
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; CHECK-DAG: v[[V35:[0-9]+]].uh = vcl0(v[[V32]].uh)
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; CHECK: v[[V36:[0-9]+]].b = vpacke(v[[V34]].h,v[[V35]].h)
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; CHECK: v0.b = vsub(v[[V36]].b,v[[V33]].b)
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define <128 x i8> @f3(<128 x i8> %a0) #0 {
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%t0 = call <128 x i8> @llvm.ctlz.v128i8(<128 x i8> %a0)
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ret <128 x i8> %t0
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}
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; CHECK-LABEL: f4
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; CHECK: v0.uh = vcl0(v0.uh)
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define <64 x i16> @f4(<64 x i16> %a0) #0 {
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%t0 = call <64 x i16> @llvm.ctlz.v64i16(<64 x i16> %a0)
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ret <64 x i16> %t0
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}
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; CHECK-LABEL: f5
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; CHECK: v0.uw = vcl0(v0.uw)
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define <32 x i32> @f5(<32 x i32> %a0) #0 {
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%t0 = call <32 x i32> @llvm.ctlz.v32i32(<32 x i32> %a0)
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ret <32 x i32> %t0
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}
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; CHECK-LABEL: f6
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; r = 0x01010101
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; CHECK-DAG: r[[R60:[0-9]+]] = ##16843009
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; CHECK-DAG: v[[V61:[0-9]+]] = vnot(v0)
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; r = 0x08080808
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; CHECK-DAG: r[[R62:[0-9]+]] = ##134744072
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; CHECK: v[[V63:[0-9]+]] = vsplat(r[[R60]])
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; CHECK-DAG: v[[V64:[0-9]+]] = vsplat(r[[R62]])
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; CHECK: v[[V65:[0-9]+]].b = vsub(v0.b,v[[V63]].b)
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; CHECK: v[[V66:[0-9]+]] = vand(v[[V61]],v[[V65]])
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; Ctlz:
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; CHECK: v[[V67:[0-9]+]]:[[V68:[0-9]+]].uh = vunpack(v[[V66]].ub)
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; CHECK: v[[V69:[0-9]+]].uh = vcl0(v[[V68]].uh)
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; CHECK: v[[V6A:[0-9]+]].uh = vcl0(v[[V67]].uh)
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; CHECK: v[[V6B:[0-9]+]].b = vpacke(v[[V6A]].h,v[[V69]].h)
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; CHECK: v[[V6C:[0-9]+]].b = vsub(v[[V6B]].b,v[[V64]].b)
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; CHECK: v0.b = vsub(v[[V64]].b,v[[V6C]].b)
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define <128 x i8> @f6(<128 x i8> %a0) #0 {
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%t0 = call <128 x i8> @llvm.cttz.v128i8(<128 x i8> %a0)
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ret <128 x i8> %t0
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}
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; CHECK-LABEL: f7
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; r = 0x00010001
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; CHECK-DAG: r[[R70:[0-9]+]] = ##65537
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; CHECK-DAG: v[[V71:[0-9]+]] = vnot(v0)
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; r = 0x00100010 // halfword bitwidths
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; CHECK-DAG: r[[R72:[0-9]+]] = ##1048592
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; CHECK: v[[V73:[0-9]+]] = vsplat(r[[R70]])
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; CHECK: v[[V74:[0-9]+]] = vsplat(r[[R72]])
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; CHECK: v[[V75:[0-9]+]].h = vsub(v0.h,v[[V73]].h)
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; CHECK: v[[V76:[0-9]+]] = vand(v[[V71]],v[[V75]])
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; Ctlz:
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; CHECK: v[[V77:[0-9]+]].uh = vcl0(v[[V76]].uh)
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; CHECK: v0.h = vsub(v[[V74]].h,v[[V77]].h)
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define <64 x i16> @f7(<64 x i16> %a0) #0 {
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%t0 = call <64 x i16> @llvm.cttz.v64i16(<64 x i16> %a0)
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ret <64 x i16> %t0
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}
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; CHECK-LABEL: f8
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; CHECK-DAG: r[[R80:[0-9]+]] = #1
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; CHECK-DAG: v[[V81:[0-9]+]] = vnot(v0)
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; CHECK-DAG: r[[R82:[0-9]+]] = #32
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; CHECK: v[[V83:[0-9]+]] = vsplat(r[[R80]])
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; CHECK: v[[V84:[0-9]+]] = vsplat(r[[R82]])
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; CHECK: v[[V85:[0-9]+]].w = vsub(v0.w,v[[V83]].w)
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; CHECK: v[[V86:[0-9]+]] = vand(v[[V81]],v[[V85]])
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; Ctlz:
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; CHECK: v[[V87:[0-9]+]].uw = vcl0(v[[V86]].uw)
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; CHECK: v0.w = vsub(v[[V84]].w,v[[V87]].w)
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define <32 x i32> @f8(<32 x i32> %a0) #0 {
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%t0 = call <32 x i32> @llvm.cttz.v32i32(<32 x i32> %a0)
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ret <32 x i32> %t0
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}
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declare <128 x i8> @llvm.ctpop.v128i8(<128 x i8>) #0
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declare <64 x i16> @llvm.ctpop.v64i16(<64 x i16>) #0
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declare <32 x i32> @llvm.ctpop.v32i32(<32 x i32>) #0
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declare <128 x i8> @llvm.ctlz.v128i8(<128 x i8>) #0
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declare <64 x i16> @llvm.ctlz.v64i16(<64 x i16>) #0
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declare <32 x i32> @llvm.ctlz.v32i32(<32 x i32>) #0
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declare <128 x i8> @llvm.cttz.v128i8(<128 x i8>) #0
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declare <64 x i16> @llvm.cttz.v64i16(<64 x i16>) #0
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declare <32 x i32> @llvm.cttz.v32i32(<32 x i32>) #0
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attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-packets" }
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@ -0,0 +1,125 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: f0
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; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vunpack(v0.ub)
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; CHECK-DAG: v[[V02:[0-9]+]].h = vpopcount(v[[V00]].h)
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; CHECK-DAG: v[[V03:[0-9]+]].h = vpopcount(v[[V01]].h)
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; CHECK: v0.b = vpacke(v[[V02]].h,v[[V03]].h)
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define <64 x i8> @f0(<64 x i8> %a0) #0 {
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%t0 = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %a0)
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ret <64 x i8> %t0
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}
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; CHECK-LABEL: f1
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; CHECK: v0.h = vpopcount(v0.h)
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define <32 x i16> @f1(<32 x i16> %a0) #0 {
|
||||
%t0 = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %a0)
|
||||
ret <32 x i16> %t0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f2
|
||||
; CHECK: v[[V20:[0-9]+]].h = vpopcount(v0.h)
|
||||
; CHECK: v[[V21:[0-9]+]]:[[V22:[0-9]+]].uw = vzxt(v[[V20]].uh)
|
||||
; CHECK: v0.w = vadd(v[[V22]].w,v[[V21]].w)
|
||||
define <16 x i32> @f2(<16 x i32> %a0) #0 {
|
||||
%t0 = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %a0)
|
||||
ret <16 x i32> %t0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f3
|
||||
; CHECK-DAG: r[[R30:[0-9]+]] = ##134744072
|
||||
; CHECK-DAG: v[[V31:[0-9]+]]:[[V32:[0-9]+]].uh = vunpack(v0.ub)
|
||||
; CHECK: v[[V33:[0-9]+]] = vsplat(r[[R30]])
|
||||
; CHECK-DAG: v[[V34:[0-9]+]].uh = vcl0(v[[V31]].uh)
|
||||
; CHECK-DAG: v[[V35:[0-9]+]].uh = vcl0(v[[V32]].uh)
|
||||
; CHECK: v[[V36:[0-9]+]].b = vpacke(v[[V34]].h,v[[V35]].h)
|
||||
; CHECK: v0.b = vsub(v[[V36]].b,v[[V33]].b)
|
||||
define <64 x i8> @f3(<64 x i8> %a0) #0 {
|
||||
%t0 = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %a0)
|
||||
ret <64 x i8> %t0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f4
|
||||
; CHECK: v0.uh = vcl0(v0.uh)
|
||||
define <32 x i16> @f4(<32 x i16> %a0) #0 {
|
||||
%t0 = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %a0)
|
||||
ret <32 x i16> %t0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f5
|
||||
; CHECK: v0.uw = vcl0(v0.uw)
|
||||
define <16 x i32> @f5(<16 x i32> %a0) #0 {
|
||||
%t0 = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a0)
|
||||
ret <16 x i32> %t0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f6
|
||||
; r = 0x01010101
|
||||
; CHECK-DAG: r[[R60:[0-9]+]] = ##16843009
|
||||
; CHECK-DAG: v[[V61:[0-9]+]] = vnot(v0)
|
||||
; r = 0x08080808
|
||||
; CHECK-DAG: r[[R62:[0-9]+]] = ##134744072
|
||||
; CHECK: v[[V63:[0-9]+]] = vsplat(r[[R60]])
|
||||
; CHECK-DAG: v[[V64:[0-9]+]] = vsplat(r[[R62]])
|
||||
; CHECK: v[[V65:[0-9]+]].b = vsub(v0.b,v[[V63]].b)
|
||||
; CHECK: v[[V66:[0-9]+]] = vand(v[[V61]],v[[V65]])
|
||||
; Ctlz:
|
||||
; CHECK: v[[V67:[0-9]+]]:[[V68:[0-9]+]].uh = vunpack(v[[V66]].ub)
|
||||
; CHECK: v[[V69:[0-9]+]].uh = vcl0(v[[V68]].uh)
|
||||
; CHECK: v[[V6A:[0-9]+]].uh = vcl0(v[[V67]].uh)
|
||||
; CHECK: v[[V6B:[0-9]+]].b = vpacke(v[[V6A]].h,v[[V69]].h)
|
||||
; CHECK: v[[V6C:[0-9]+]].b = vsub(v[[V6B]].b,v[[V64]].b)
|
||||
; CHECK: v0.b = vsub(v[[V64]].b,v[[V6C]].b)
|
||||
define <64 x i8> @f6(<64 x i8> %a0) #0 {
|
||||
%t0 = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %a0)
|
||||
ret <64 x i8> %t0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f7
|
||||
; r = 0x00010001
|
||||
; CHECK-DAG: r[[R70:[0-9]+]] = ##65537
|
||||
; CHECK-DAG: v[[V71:[0-9]+]] = vnot(v0)
|
||||
; r = 0x00100010 // halfword bitwidths
|
||||
; CHECK-DAG: r[[R72:[0-9]+]] = ##1048592
|
||||
; CHECK: v[[V73:[0-9]+]] = vsplat(r[[R70]])
|
||||
; CHECK: v[[V74:[0-9]+]] = vsplat(r[[R72]])
|
||||
; CHECK: v[[V75:[0-9]+]].h = vsub(v0.h,v[[V73]].h)
|
||||
; CHECK: v[[V76:[0-9]+]] = vand(v[[V71]],v[[V75]])
|
||||
; Ctlz:
|
||||
; CHECK: v[[V77:[0-9]+]].uh = vcl0(v[[V76]].uh)
|
||||
; CHECK: v0.h = vsub(v[[V74]].h,v[[V77]].h)
|
||||
define <32 x i16> @f7(<32 x i16> %a0) #0 {
|
||||
%t0 = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %a0)
|
||||
ret <32 x i16> %t0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: f8
|
||||
; CHECK-DAG: r[[R80:[0-9]+]] = #1
|
||||
; CHECK-DAG: v[[V81:[0-9]+]] = vnot(v0)
|
||||
; CHECK-DAG: r[[R82:[0-9]+]] = #32
|
||||
; CHECK: v[[V83:[0-9]+]] = vsplat(r[[R80]])
|
||||
; CHECK: v[[V84:[0-9]+]] = vsplat(r[[R82]])
|
||||
; CHECK: v[[V85:[0-9]+]].w = vsub(v0.w,v[[V83]].w)
|
||||
; CHECK: v[[V86:[0-9]+]] = vand(v[[V81]],v[[V85]])
|
||||
; Ctlz:
|
||||
; CHECK: v[[V87:[0-9]+]].uw = vcl0(v[[V86]].uw)
|
||||
; CHECK: v0.w = vsub(v[[V84]].w,v[[V87]].w)
|
||||
define <16 x i32> @f8(<16 x i32> %a0) #0 {
|
||||
%t0 = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %a0)
|
||||
ret <16 x i32> %t0
|
||||
}
|
||||
|
||||
|
||||
declare <64 x i8> @llvm.ctpop.v64i8(<64 x i8>) #0
|
||||
declare <32 x i16> @llvm.ctpop.v32i16(<32 x i16>) #0
|
||||
declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) #0
|
||||
|
||||
declare <64 x i8> @llvm.ctlz.v64i8(<64 x i8>) #0
|
||||
declare <32 x i16> @llvm.ctlz.v32i16(<32 x i16>) #0
|
||||
declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>) #0
|
||||
|
||||
declare <64 x i8> @llvm.cttz.v64i8(<64 x i8>) #0
|
||||
declare <32 x i16> @llvm.cttz.v32i16(<32 x i16>) #0
|
||||
declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>) #0
|
||||
|
||||
attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-packets" }
|
||||
Loading…
Reference in New Issue