forked from OSchip/llvm-project
BranchFolding: Use LivePhysReg to update live in lists.
Use LivePhysRegs with a backwards walking algorithm to update live in lists, this way the results do not depend on the presence of kill flags anymore. This patch also reduces the number of registers added as live-in. Previously all pristine registers as well as all sub registers of a super register were added resulting in unnecessarily large live in lists. This fixed https://llvm.org/PR25263. Differential Revision: http://reviews.llvm.org/D22027 llvm-svn: 275201
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@ -32,7 +32,6 @@
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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@ -212,13 +211,10 @@ bool BranchFolder::OptimizeFunction(MachineFunction &MF,
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TRI = tri;
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MMI = mmi;
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MLI = mli;
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RS = nullptr;
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// Use a RegScavenger to help update liveness when required.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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if (MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
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RS = new RegScavenger();
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else
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UpdateLiveIns = MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF);
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if (!UpdateLiveIns)
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MRI.invalidateLiveness();
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// Fix CFG. The later algorithms expect it to be right.
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@ -249,10 +245,8 @@ bool BranchFolder::OptimizeFunction(MachineFunction &MF,
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// See if any jump tables have become dead as the code generator
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// did its thing.
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MachineJumpTableInfo *JTI = MF.getJumpTableInfo();
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if (!JTI) {
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delete RS;
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if (!JTI)
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return MadeChange;
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}
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// Walk the function to find jump tables that are live.
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BitVector JTIsLive(JTI->getJumpTables().size());
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@ -274,7 +268,6 @@ bool BranchFolder::OptimizeFunction(MachineFunction &MF,
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MadeChange = true;
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}
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delete RS;
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return MadeChange;
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}
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@ -406,15 +399,27 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1,
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return TailLen;
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}
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void BranchFolder::MaintainLiveIns(MachineBasicBlock *CurMBB,
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MachineBasicBlock *NewMBB) {
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if (RS) {
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RS->enterBasicBlock(*CurMBB);
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if (!CurMBB->empty())
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RS->forward(std::prev(CurMBB->end()));
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for (unsigned int i = 1, e = TRI->getNumRegs(); i != e; i++)
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if (RS->isRegUsed(i, false))
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NewMBB->addLiveIn(i);
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void BranchFolder::computeLiveIns(MachineBasicBlock &MBB) {
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if (!UpdateLiveIns)
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return;
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LiveRegs.init(TRI);
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LiveRegs.addLiveOutsNoPristines(MBB);
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for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend()))
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LiveRegs.stepBackward(MI);
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for (unsigned Reg : LiveRegs) {
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// Skip the register if we are about to add one of its super registers.
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bool ContainsSuperReg = false;
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for (MCSuperRegIterator SReg(Reg, TRI); SReg.isValid(); ++SReg) {
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if (LiveRegs.contains(*SReg)) {
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ContainsSuperReg = true;
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break;
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}
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}
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if (ContainsSuperReg)
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continue;
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MBB.addLiveIn(Reg);
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}
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}
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@ -422,12 +427,9 @@ void BranchFolder::MaintainLiveIns(MachineBasicBlock *CurMBB,
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/// after it, replacing it with an unconditional branch to NewDest.
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void BranchFolder::ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
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MachineBasicBlock *NewDest) {
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MachineBasicBlock *CurMBB = OldInst->getParent();
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TII->ReplaceTailWithBranchTo(OldInst, NewDest);
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// For targets that use the register scavenger, we must maintain LiveIns.
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MaintainLiveIns(CurMBB, NewDest);
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computeLiveIns(*NewDest);
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++NumTailMerge;
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}
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@ -465,8 +467,7 @@ MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
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// NewMBB inherits CurMBB's block frequency.
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MBBFreqInfo.setBlockFreq(NewMBB, MBBFreqInfo.getBlockFreq(&CurMBB));
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// For targets that use the register scavenger, we must maintain LiveIns.
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MaintainLiveIns(&CurMBB, NewMBB);
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computeLiveIns(*NewMBB);
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// Add the new block to the funclet.
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const auto &FuncletI = FuncletMembership.find(&CurMBB);
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@ -11,6 +11,7 @@
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#define LLVM_LIB_CODEGEN_BRANCHFOLDING_H
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Support/BlockFrequency.h"
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#include <vector>
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@ -21,7 +22,6 @@ namespace llvm {
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class MachineFunction;
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class MachineModuleInfo;
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class MachineLoopInfo;
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class RegScavenger;
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class TargetInstrInfo;
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class TargetRegisterInfo;
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@ -98,11 +98,12 @@ namespace llvm {
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bool AfterBlockPlacement;
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bool EnableTailMerge;
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bool EnableHoistCommonCode;
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bool UpdateLiveIns;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineModuleInfo *MMI;
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MachineLoopInfo *MLI;
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RegScavenger *RS;
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LivePhysRegs LiveRegs;
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public:
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/// \brief This class keeps track of branch frequencies of newly created
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@ -130,8 +131,7 @@ namespace llvm {
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bool TryTailMergeBlocks(MachineBasicBlock* SuccBB,
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MachineBasicBlock* PredBB);
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void setCommonTailEdgeWeights(MachineBasicBlock &TailMBB);
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void MaintainLiveIns(MachineBasicBlock *CurMBB,
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MachineBasicBlock *NewMBB);
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void computeLiveIns(MachineBasicBlock &MBB);
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void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
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MachineBasicBlock *NewDest);
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MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB,
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