diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index a0e6bbe33ee8..501f015ed730 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -21,7 +21,7 @@ define <4 x i32> @shl_non_splat_vector(<4 x i32> %A) {
 
 define i32 @test6(i32 %A) {
 ; CHECK-LABEL: @test6(
-; CHECK-NEXT:    [[C:%.*]] = mul i32 %A, 6
+; CHECK-NEXT:    [[C:%.*]] = mul i32 [[A:%.*]], 6
 ; CHECK-NEXT:    ret i32 [[C]]
 ;
   %B = shl i32 %A, 1      ;; convert to an mul instruction
@@ -31,7 +31,7 @@ define i32 @test6(i32 %A) {
 
 define i32 @test6a(i32 %A) {
 ; CHECK-LABEL: @test6a(
-; CHECK-NEXT:    [[C:%.*]] = mul i32 %A, 6
+; CHECK-NEXT:    [[C:%.*]] = mul i32 [[A:%.*]], 6
 ; CHECK-NEXT:    ret i32 [[C]]
 ;
   %B = mul i32 %A, 3
@@ -52,7 +52,7 @@ define i8 @test8(i8 %A) {
 ;; (A << 7) >> 7 === A & 1
 define i8 @test9(i8 %A) {
 ; CHECK-LABEL: @test9(
-; CHECK-NEXT:    [[B:%.*]] = and i8 %A, 1
+; CHECK-NEXT:    [[B:%.*]] = and i8 [[A:%.*]], 1
 ; CHECK-NEXT:    ret i8 [[B]]
 ;
   %B = shl i8 %A, 7
@@ -64,7 +64,7 @@ define i8 @test9(i8 %A) {
 
 define i8 @test10(i8 %A) {
 ; CHECK-LABEL: @test10(
-; CHECK-NEXT:    [[B:%.*]] = and i8 %A, -128
+; CHECK-NEXT:    [[B:%.*]] = and i8 [[A:%.*]], -128
 ; CHECK-NEXT:    ret i8 [[B]]
 ;
   %B = lshr i8 %A, 7
@@ -75,7 +75,7 @@ define i8 @test10(i8 %A) {
 ;; Allow the simplification when the lshr shift is exact.
 define i8 @test10a(i8 %A) {
 ; CHECK-LABEL: @test10a(
-; CHECK-NEXT:    ret i8 %A
+; CHECK-NEXT:    ret i8 [[A:%.*]]
 ;
   %B = lshr exact i8 %A, 7
   %C = shl i8 %B, 7
@@ -85,14 +85,14 @@ define i8 @test10a(i8 %A) {
 ;; This transformation is deferred to DAGCombine:
 ;; (A >> 3) << 4 === (A & 0x1F) << 1
 ;; The shl may be valuable to scalar evolution.
-define i8 @test11(i8 %A) {
+define i8 @test11(i8 %x) {
 ; CHECK-LABEL: @test11(
-; CHECK-NEXT:    [[A:%.*]] = mul i8 %A, 3
+; CHECK-NEXT:    [[A:%.*]] = mul i8 [[X:%.*]], 3
 ; CHECK-NEXT:    [[B:%.*]] = lshr i8 [[A]], 3
 ; CHECK-NEXT:    [[C:%.*]] = shl i8 [[B]], 4
 ; CHECK-NEXT:    ret i8 [[C]]
 ;
-  %a = mul i8 %A, 3
+  %a = mul i8 %x, 3
   %B = lshr i8 %a, 3
   %C = shl i8 %B, 4
   ret i8 %C
@@ -101,7 +101,7 @@ define i8 @test11(i8 %A) {
 ;; Allow the simplification in InstCombine when the lshr shift is exact.
 define i8 @test11a(i8 %A) {
 ; CHECK-LABEL: @test11a(
-; CHECK-NEXT:    [[C:%.*]] = mul i8 %A, 6
+; CHECK-NEXT:    [[C:%.*]] = mul i8 [[A:%.*]], 6
 ; CHECK-NEXT:    ret i8 [[C]]
 ;
   %a = mul i8 %A, 3
@@ -114,8 +114,8 @@ define i8 @test11a(i8 %A) {
 ;; (A >> 8) << 8 === A & -256
 define i32 @test12(i32 %A) {
 ; CHECK-LABEL: @test12(
-; CHECK-NEXT:    [[B1:%.*]] = and i32 %A, -256
-; CHECK-NEXT:    ret i32 [[B1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], -256
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %B = ashr i32 %A, 8
   %C = shl i32 %B, 8
@@ -141,14 +141,14 @@ define i8 @shishi(i8 %x) {
 ;; This transformation is deferred to DAGCombine:
 ;; (A >> 3) << 4 === (A & -8) * 2
 ;; The shl may be valuable to scalar evolution.
-define i8 @test13(i8 %A) {
+define i8 @test13(i8 %x) {
 ; CHECK-LABEL: @test13(
-; CHECK-NEXT:    [[A:%.*]] = mul i8 %A, 3
-; CHECK-NEXT:    [[B1:%.*]] = lshr i8 [[A]], 3
-; CHECK-NEXT:    [[C:%.*]] = shl i8 [[B1]], 4
+; CHECK-NEXT:    [[A:%.*]] = mul i8 [[X:%.*]], 3
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i8 [[A]], 3
+; CHECK-NEXT:    [[C:%.*]] = shl i8 [[TMP1]], 4
 ; CHECK-NEXT:    ret i8 [[C]]
 ;
-  %a = mul i8 %A, 3
+  %a = mul i8 %x, 3
   %B = ashr i8 %a, 3
   %C = shl i8 %B, 4
   ret i8 %C
@@ -156,7 +156,7 @@ define i8 @test13(i8 %A) {
 
 define i8 @test13a(i8 %A) {
 ; CHECK-LABEL: @test13a(
-; CHECK-NEXT:    [[C:%.*]] = mul i8 %A, 6
+; CHECK-NEXT:    [[C:%.*]] = mul i8 [[A:%.*]], 6
 ; CHECK-NEXT:    ret i8 [[C]]
 ;
   %a = mul i8 %A, 3
@@ -168,7 +168,7 @@ define i8 @test13a(i8 %A) {
 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
 define i32 @test14(i32 %A) {
 ; CHECK-LABEL: @test14(
-; CHECK-NEXT:    [[B:%.*]] = and i32 %A, -19760
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[A:%.*]], -19760
 ; CHECK-NEXT:    [[C:%.*]] = or i32 [[B]], 19744
 ; CHECK-NEXT:    ret i32 [[C]]
 ;
@@ -181,7 +181,7 @@ define i32 @test14(i32 %A) {
 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
 define i32 @test14a(i32 %A) {
 ; CHECK-LABEL: @test14a(
-; CHECK-NEXT:    [[C:%.*]] = and i32 %A, 77
+; CHECK-NEXT:    [[C:%.*]] = and i32 [[A:%.*]], 77
 ; CHECK-NEXT:    ret i32 [[C]]
 ;
   %B = shl i32 %A, 4
@@ -192,7 +192,7 @@ define i32 @test14a(i32 %A) {
 
 define i32 @test15(i1 %C) {
 ; CHECK-LABEL: @test15(
-; CHECK-NEXT:    [[A:%.*]] = select i1 %C, i32 12, i32 4
+; CHECK-NEXT:    [[A:%.*]] = select i1 [[C:%.*]], i32 12, i32 4
 ; CHECK-NEXT:    ret i32 [[A]]
 ;
   %A = select i1 %C, i32 3, i32 1
@@ -202,7 +202,7 @@ define i32 @test15(i1 %C) {
 
 define i32 @test15a(i1 %C) {
 ; CHECK-LABEL: @test15a(
-; CHECK-NEXT:    [[V:%.*]] = select i1 %C, i32 512, i32 128
+; CHECK-NEXT:    [[V:%.*]] = select i1 [[C:%.*]], i32 512, i32 128
 ; CHECK-NEXT:    ret i32 [[V]]
 ;
   %A = select i1 %C, i8 3, i8 1
@@ -213,7 +213,7 @@ define i32 @test15a(i1 %C) {
 
 define i1 @test16(i32 %X) {
 ; CHECK-LABEL: @test16(
-; CHECK-NEXT:    [[TMP_6:%.*]] = and i32 %X, 16
+; CHECK-NEXT:    [[TMP_6:%.*]] = and i32 [[X:%.*]], 16
 ; CHECK-NEXT:    [[TMP_7:%.*]] = icmp ne i32 [[TMP_6]], 0
 ; CHECK-NEXT:    ret i1 [[TMP_7]]
 ;
@@ -225,7 +225,7 @@ define i1 @test16(i32 %X) {
 
 define i1 @test17(i32 %A) {
 ; CHECK-LABEL: @test17(
-; CHECK-NEXT:    [[B_MASK:%.*]] = and i32 %A, -8
+; CHECK-NEXT:    [[B_MASK:%.*]] = and i32 [[A:%.*]], -8
 ; CHECK-NEXT:    [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
@@ -236,7 +236,7 @@ define i1 @test17(i32 %A) {
 
 define <2 x i1> @test17vec(<2 x i32> %A) {
 ; CHECK-LABEL: @test17vec(
-; CHECK-NEXT:    [[B_MASK:%.*]] = and <2 x i32> %A, <i32 -8, i32 -8>
+; CHECK-NEXT:    [[B_MASK:%.*]] = and <2 x i32> [[A:%.*]], <i32 -8, i32 -8>
 ; CHECK-NEXT:    [[C:%.*]] = icmp eq <2 x i32> [[B_MASK]], <i32 9872, i32 9872>
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
@@ -257,7 +257,7 @@ define i1 @test18(i8 %A) {
 
 define i1 @test19(i32 %A) {
 ; CHECK-LABEL: @test19(
-; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 %A, 4
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[A:%.*]], 4
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %B = ashr i32 %A, 2
@@ -268,7 +268,7 @@ define i1 @test19(i32 %A) {
 
 define <2 x i1> @test19vec(<2 x i32> %A) {
 ; CHECK-LABEL: @test19vec(
-; CHECK-NEXT:    [[C:%.*]] = icmp ult <2 x i32> %A, <i32 4, i32 4>
+; CHECK-NEXT:    [[C:%.*]] = icmp ult <2 x i32> [[A:%.*]], <i32 4, i32 4>
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %B = ashr <2 x i32> %A, <i32 2, i32 2>
@@ -279,7 +279,7 @@ define <2 x i1> @test19vec(<2 x i32> %A) {
 ;; X >u ~4
 define i1 @test19a(i32 %A) {
 ; CHECK-LABEL: @test19a(
-; CHECK-NEXT:    [[C:%.*]] = icmp ugt i32 %A, -5
+; CHECK-NEXT:    [[C:%.*]] = icmp ugt i32 [[A:%.*]], -5
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
   %B = ashr i32 %A, 2
@@ -289,7 +289,7 @@ define i1 @test19a(i32 %A) {
 
 define <2 x i1> @test19a_vec(<2 x i32> %A) {
 ; CHECK-LABEL: @test19a_vec(
-; CHECK-NEXT:    [[C:%.*]] = icmp ugt <2 x i32> %A, <i32 -5, i32 -5>
+; CHECK-NEXT:    [[C:%.*]] = icmp ugt <2 x i32> [[A:%.*]], <i32 -5, i32 -5>
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %B = ashr <2 x i32> %A, <i32 2, i32 2>
@@ -309,7 +309,7 @@ define i1 @test20(i8 %A) {
 
 define i1 @test21(i8 %A) {
 ; CHECK-LABEL: @test21(
-; CHECK-NEXT:    [[B_MASK:%.*]] = and i8 %A, 15
+; CHECK-NEXT:    [[B_MASK:%.*]] = and i8 [[A:%.*]], 15
 ; CHECK-NEXT:    [[C:%.*]] = icmp eq i8 [[B_MASK]], 8
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
@@ -320,7 +320,7 @@ define i1 @test21(i8 %A) {
 
 define i1 @test22(i8 %A) {
 ; CHECK-LABEL: @test22(
-; CHECK-NEXT:    [[B_MASK:%.*]] = and i8 %A, 15
+; CHECK-NEXT:    [[B_MASK:%.*]] = and i8 [[A:%.*]], 15
 ; CHECK-NEXT:    [[C:%.*]] = icmp eq i8 [[B_MASK]], 0
 ; CHECK-NEXT:    ret i1 [[C]]
 ;
@@ -331,7 +331,7 @@ define i1 @test22(i8 %A) {
 
 define i8 @test23(i32 %A) {
 ; CHECK-LABEL: @test23(
-; CHECK-NEXT:    [[D:%.*]] = trunc i32 %A to i8
+; CHECK-NEXT:    [[D:%.*]] = trunc i32 [[A:%.*]] to i8
 ; CHECK-NEXT:    ret i8 [[D]]
 ;
   ;; casts not needed
@@ -343,7 +343,7 @@ define i8 @test23(i32 %A) {
 
 define i8 @test24(i8 %X) {
 ; CHECK-LABEL: @test24(
-; CHECK-NEXT:    [[Z:%.*]] = and i8 %X, 3
+; CHECK-NEXT:    [[Z:%.*]] = and i8 [[X:%.*]], 3
 ; CHECK-NEXT:    ret i8 [[Z]]
 ;
   %Y = and i8 %X, -5
@@ -354,8 +354,8 @@ define i8 @test24(i8 %X) {
 
 define i32 @test25(i32 %tmp.2, i32 %AA) {
 ; CHECK-LABEL: @test25(
-; CHECK-NEXT:    [[TMP_3:%.*]] = and i32 %tmp.2, -131072
-; CHECK-NEXT:    [[X2:%.*]] = add i32 [[TMP_3]], %AA
+; CHECK-NEXT:    [[TMP_3:%.*]] = and i32 [[TMP_2:%.*]], -131072
+; CHECK-NEXT:    [[X2:%.*]] = add i32 [[TMP_3]], [[AA:%.*]]
 ; CHECK-NEXT:    [[TMP_6:%.*]] = and i32 [[X2]], -131072
 ; CHECK-NEXT:    ret i32 [[TMP_6]]
 ;
@@ -368,8 +368,8 @@ define i32 @test25(i32 %tmp.2, i32 %AA) {
 
 define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) {
 ; CHECK-LABEL: @test25_vector(
-; CHECK-NEXT:    [[TMP_3:%.*]] = and <2 x i32> %tmp.2, <i32 -131072, i32 -131072>
-; CHECK-NEXT:    [[X2:%.*]] = add <2 x i32> [[TMP_3]], %AA
+; CHECK-NEXT:    [[TMP_3:%.*]] = and <2 x i32> [[TMP_2:%.*]], <i32 -131072, i32 -131072>
+; CHECK-NEXT:    [[X2:%.*]] = add <2 x i32> [[TMP_3]], [[AA:%.*]]
 ; CHECK-NEXT:    [[TMP_6:%.*]] = and <2 x i32> [[X2]], <i32 -131072, i32 -131072>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP_6]]
 ;
@@ -383,7 +383,7 @@ define <2 x i32> @test25_vector(<2 x i32> %tmp.2, <2 x i32> %AA) {
 ;; handle casts between shifts.
 define i32 @test26(i32 %A) {
 ; CHECK-LABEL: @test26(
-; CHECK-NEXT:    [[B:%.*]] = and i32 %A, -2
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[A:%.*]], -2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %B = lshr i32 %A, 1
@@ -395,7 +395,7 @@ define i32 @test26(i32 %A) {
 
 define i1 @test27(i32 %x) nounwind {
 ; CHECK-LABEL: @test27(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 %x, 8
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 8
 ; CHECK-NEXT:    [[Z:%.*]] = icmp ne i32 [[TMP1]], 0
 ; CHECK-NEXT:    ret i1 [[Z]]
 ;
@@ -406,7 +406,7 @@ define i1 @test27(i32 %x) nounwind {
 
 define i1 @test28(i8 %x) {
 ; CHECK-LABEL: @test28(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 %x, 0
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %shr = lshr i8 %x, 7
@@ -416,7 +416,7 @@ define i1 @test28(i8 %x) {
 
 define <2 x i1> @test28vec(<2 x i8> %x) {
 ; CHECK-LABEL: @test28vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> %x, zeroinitializer
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[CMP]]
 ;
   %shr = lshr <2 x i8> %x, <i8 7, i8 7>
@@ -427,13 +427,13 @@ define <2 x i1> @test28vec(<2 x i8> %x) {
 define i8 @test28a(i8 %x, i8 %y) {
 ; CHECK-LABEL: @test28a(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr i8 %x, 7
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i8 [[X:%.*]], 7
 ; CHECK-NEXT:    [[COND1:%.*]] = icmp eq i8 [[TMP1]], 0
-; CHECK-NEXT:    br i1 [[COND1]], label %bb2, label %bb1
+; CHECK-NEXT:    br i1 [[COND1]], label [[BB2:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    ret i8 [[TMP1]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[TMP1]], %y
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[TMP1]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i8 [[TMP2]]
 ;
 entry:
@@ -452,7 +452,7 @@ bb2:
 define i32 @test29(i64 %d18) {
 ; CHECK-LABEL: @test29(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP916:%.*]] = lshr i64 %d18, 63
+; CHECK-NEXT:    [[TMP916:%.*]] = lshr i64 [[D18:%.*]], 63
 ; CHECK-NEXT:    [[TMP10:%.*]] = trunc i64 [[TMP916]] to i32
 ; CHECK-NEXT:    ret i32 [[TMP10]]
 ;
@@ -466,8 +466,8 @@ entry:
 
 define i32 @test30(i32 %A, i32 %B, i32 %C) {
 ; CHECK-LABEL: @test30(
-; CHECK-NEXT:    [[X1:%.*]] = and i32 %A, %B
-; CHECK-NEXT:    [[Z:%.*]] = shl i32 [[X1]], %C
+; CHECK-NEXT:    [[X1:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = shl i32 [[X1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %X = shl i32 %A, %C
@@ -478,8 +478,8 @@ define i32 @test30(i32 %A, i32 %B, i32 %C) {
 
 define i32 @test31(i32 %A, i32 %B, i32 %C) {
 ; CHECK-LABEL: @test31(
-; CHECK-NEXT:    [[X1:%.*]] = or i32 %A, %B
-; CHECK-NEXT:    [[Z:%.*]] = lshr i32 [[X1]], %C
+; CHECK-NEXT:    [[X1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = lshr i32 [[X1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %X = lshr i32 %A, %C
@@ -490,8 +490,8 @@ define i32 @test31(i32 %A, i32 %B, i32 %C) {
 
 define i32 @test32(i32 %A, i32 %B, i32 %C) {
 ; CHECK-LABEL: @test32(
-; CHECK-NEXT:    [[X1:%.*]] = xor i32 %A, %B
-; CHECK-NEXT:    [[Z:%.*]] = ashr i32 [[X1]], %C
+; CHECK-NEXT:    [[X1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[Z:%.*]] = ashr i32 [[X1]], [[C:%.*]]
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %X = ashr i32 %A, %C
@@ -502,7 +502,7 @@ define i32 @test32(i32 %A, i32 %B, i32 %C) {
 
 define i1 @test33(i32 %X) {
 ; CHECK-LABEL: @test33(
-; CHECK-NEXT:    [[TMP1_MASK:%.*]] = and i32 %X, 16777216
+; CHECK-NEXT:    [[TMP1_MASK:%.*]] = and i32 [[X:%.*]], 16777216
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1_MASK]], 0
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
@@ -513,7 +513,7 @@ define i1 @test33(i32 %X) {
 
 define <2 x i1> @test33vec(<2 x i32> %X) {
 ; CHECK-LABEL: @test33vec(
-; CHECK-NEXT:    [[TMP1_MASK:%.*]] = and <2 x i32> %X, <i32 16777216, i32 16777216>
+; CHECK-NEXT:    [[TMP1_MASK:%.*]] = and <2 x i32> [[X:%.*]], <i32 16777216, i32 16777216>
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1_MASK]], zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
 ;
@@ -533,7 +533,7 @@ define i1 @test34(i32 %X) {
 
 define i1 @test35(i32 %X) {
 ; CHECK-LABEL: @test35(
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 %X, 0
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X:%.*]], 0
 ; CHECK-NEXT:    ret i1 [[TMP2]]
 ;
   %tmp1 = ashr i32 %X, 7
@@ -543,7 +543,7 @@ define i1 @test35(i32 %X) {
 
 define <2 x i1> @test35vec(<2 x i32> %X) {
 ; CHECK-LABEL: @test35vec(
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> %X, zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
 ;
   %tmp1 = ashr <2 x i32> %X, <i32 7, i32 7>
@@ -553,7 +553,7 @@ define <2 x i1> @test35vec(<2 x i32> %X) {
 
 define i128 @test36(i128 %A, i128 %B) {
 ; CHECK-LABEL: @test36(
-; CHECK-NEXT:    [[TMP231:%.*]] = or i128 %B, %A
+; CHECK-NEXT:    [[TMP231:%.*]] = or i128 [[B:%.*]], [[A:%.*]]
 ; CHECK-NEXT:    [[INS:%.*]] = and i128 [[TMP231]], 18446744073709551615
 ; CHECK-NEXT:    ret i128 [[INS]]
 ;
@@ -566,9 +566,9 @@ define i128 @test36(i128 %A, i128 %B) {
 
 define i64 @test37(i128 %A, i32 %B) {
 ; CHECK-LABEL: @test37(
-; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 %B to i128
+; CHECK-NEXT:    [[TMP22:%.*]] = zext i32 [[B:%.*]] to i128
 ; CHECK-NEXT:    [[TMP23:%.*]] = shl nuw nsw i128 [[TMP22]], 32
-; CHECK-NEXT:    [[INS:%.*]] = or i128 [[TMP23]], %A
+; CHECK-NEXT:    [[INS:%.*]] = or i128 [[TMP23]], [[A:%.*]]
 ; CHECK-NEXT:    [[TMP46:%.*]] = trunc i128 [[INS]] to i64
 ; CHECK-NEXT:    ret i64 [[TMP46]]
 ;
@@ -583,7 +583,7 @@ define i64 @test37(i128 %A, i32 %B) {
 
 define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) {
 ; CHECK-LABEL: @shl_nuw_nsw_splat_vec(
-; CHECK-NEXT:    [[T2:%.*]] = zext <2 x i8> %x to <2 x i32>
+; CHECK-NEXT:    [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
 ; CHECK-NEXT:    [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17>
 ; CHECK-NEXT:    ret <2 x i32> [[T3]]
 ;
@@ -594,7 +594,7 @@ define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) {
 
 define i32 @test38(i32 %x) nounwind readnone {
 ; CHECK-LABEL: @test38(
-; CHECK-NEXT:    [[REM1:%.*]] = and i32 %x, 31
+; CHECK-NEXT:    [[REM1:%.*]] = and i32 [[X:%.*]], 31
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 1, [[REM1]]
 ; CHECK-NEXT:    ret i32 [[SHL]]
 ;
@@ -607,7 +607,7 @@ define i32 @test38(i32 %x) nounwind readnone {
 define i8 @test39(i32 %a0) {
 ; CHECK-LABEL: @test39(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP4:%.*]] = trunc i32 %a0 to i8
+; CHECK-NEXT:    [[TMP4:%.*]] = trunc i32 [[A0:%.*]] to i8
 ; CHECK-NEXT:    [[TMP5:%.*]] = shl i8 [[TMP4]], 5
 ; CHECK-NEXT:    [[TMP49:%.*]] = shl i8 [[TMP4]], 6
 ; CHECK-NEXT:    [[TMP50:%.*]] = and i8 [[TMP49]], 64
@@ -634,8 +634,8 @@ entry:
 ; PR9809
 define i32 @test40(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test40(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i32 %b, 2
-; CHECK-NEXT:    [[DIV:%.*]] = lshr i32 %a, [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[B:%.*]], 2
+; CHECK-NEXT:    [[DIV:%.*]] = lshr i32 [[A:%.*]], [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %shl1 = shl i32 1, %b
@@ -646,7 +646,7 @@ define i32 @test40(i32 %a, i32 %b) nounwind {
 
 define i32 @test41(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test41(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 8, %b
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 8, [[B:%.*]]
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %1 = shl i32 1, %b
@@ -656,8 +656,8 @@ define i32 @test41(i32 %a, i32 %b) nounwind {
 
 define i32 @test42(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test42(
-; CHECK-NEXT:    [[DIV:%.*]] = lshr exact i32 4096, %b
-; CHECK-NEXT:    [[DIV2:%.*]] = udiv i32 %a, [[DIV]]
+; CHECK-NEXT:    [[DIV:%.*]] = lshr exact i32 4096, [[B:%.*]]
+; CHECK-NEXT:    [[DIV2:%.*]] = udiv i32 [[A:%.*]], [[DIV]]
 ; CHECK-NEXT:    ret i32 [[DIV2]]
 ;
   %div = lshr i32 4096, %b    ; must be exact otherwise we'd divide by zero
@@ -667,8 +667,8 @@ define i32 @test42(i32 %a, i32 %b) nounwind {
 
 define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: @test42vec(
-; CHECK-NEXT:    [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, %b
-; CHECK-NEXT:    [[DIV2:%.*]] = udiv <2 x i32> %a, [[DIV]]
+; CHECK-NEXT:    [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, [[B:%.*]]
+; CHECK-NEXT:    [[DIV2:%.*]] = udiv <2 x i32> [[A:%.*]], [[DIV]]
 ; CHECK-NEXT:    ret <2 x i32> [[DIV2]]
 ;
   %div = lshr <2 x i32> <i32 4096, i32 4096>, %b    ; must be exact otherwise we'd divide by zero
@@ -678,8 +678,8 @@ define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) {
 
 define i32 @test43(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: @test43(
-; CHECK-NEXT:    [[TMP1:%.*]] = add i32 %b, 12
-; CHECK-NEXT:    [[DIV2:%.*]] = lshr i32 %a, [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[B:%.*]], 12
+; CHECK-NEXT:    [[DIV2:%.*]] = lshr i32 [[A:%.*]], [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[DIV2]]
 ;
   %div = shl i32 4096, %b    ; must be exact otherwise we'd divide by zero
@@ -689,7 +689,7 @@ define i32 @test43(i32 %a, i32 %b) nounwind {
 
 define i32 @test44(i32 %a) nounwind {
 ; CHECK-LABEL: @test44(
-; CHECK-NEXT:    [[Y:%.*]] = shl i32 %a, 5
+; CHECK-NEXT:    [[Y:%.*]] = shl i32 [[A:%.*]], 5
 ; CHECK-NEXT:    ret i32 [[Y]]
 ;
   %y = shl nuw i32 %a, 1
@@ -699,7 +699,7 @@ define i32 @test44(i32 %a) nounwind {
 
 define i32 @test45(i32 %a) nounwind {
 ; CHECK-LABEL: @test45(
-; CHECK-NEXT:    [[Y:%.*]] = lshr i32 %a, 5
+; CHECK-NEXT:    [[Y:%.*]] = lshr i32 [[A:%.*]], 5
 ; CHECK-NEXT:    ret i32 [[Y]]
 ;
   %y = lshr exact i32 %a, 1
@@ -711,7 +711,7 @@ define i32 @test45(i32 %a) nounwind {
 
 define i32 @test46(i32 %a) {
 ; CHECK-LABEL: @test46(
-; CHECK-NEXT:    [[Z:%.*]] = ashr exact i32 %a, 2
+; CHECK-NEXT:    [[Z:%.*]] = ashr exact i32 [[A:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[Z]]
 ;
   %y = ashr exact i32 %a, 3
@@ -723,7 +723,7 @@ define i32 @test46(i32 %a) {
 
 define <2 x i32> @test46_splat_vec(<2 x i32> %a) {
 ; CHECK-LABEL: @test46_splat_vec(
-; CHECK-NEXT:    [[Z:%.*]] = ashr exact <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT:    [[Z:%.*]] = ashr exact <2 x i32> [[A:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[Z]]
 ;
   %y = ashr exact <2 x i32> %a, <i32 3, i32 3>
@@ -735,7 +735,7 @@ define <2 x i32> @test46_splat_vec(<2 x i32> %a) {
 
 define i8 @test47(i8 %a) {
 ; CHECK-LABEL: @test47(
-; CHECK-NEXT:    [[Z:%.*]] = lshr exact i8 %a, 2
+; CHECK-NEXT:    [[Z:%.*]] = lshr exact i8 [[A:%.*]], 2
 ; CHECK-NEXT:    ret i8 [[Z]]
 ;
   %y = lshr exact i8 %a, 3
@@ -747,7 +747,7 @@ define i8 @test47(i8 %a) {
 
 define <2 x i8> @test47_splat_vec(<2 x i8> %a) {
 ; CHECK-LABEL: @test47_splat_vec(
-; CHECK-NEXT:    [[Z:%.*]] = lshr exact <2 x i8> %a, <i8 2, i8 2>
+; CHECK-NEXT:    [[Z:%.*]] = lshr exact <2 x i8> [[A:%.*]], <i8 2, i8 2>
 ; CHECK-NEXT:    ret <2 x i8> [[Z]]
 ;
   %y = lshr exact <2 x i8> %a, <i8 3, i8 3>
@@ -759,7 +759,7 @@ define <2 x i8> @test47_splat_vec(<2 x i8> %a) {
 
 define i32 @test48(i32 %x) {
 ; CHECK-LABEL: @test48(
-; CHECK-NEXT:    [[B:%.*]] = shl i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = shl i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = lshr exact i32 %x, 1
@@ -771,7 +771,7 @@ define i32 @test48(i32 %x) {
 
 define i32 @test48_nuw_nsw(i32 %x) {
 ; CHECK-LABEL: @test48_nuw_nsw(
-; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = lshr exact i32 %x, 1
@@ -783,7 +783,7 @@ define i32 @test48_nuw_nsw(i32 %x) {
 
 define <2 x i32> @test48_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test48_splat_vec(
-; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
   %A = lshr exact <2 x i32> %x, <i32 1, i32 1>
@@ -795,7 +795,7 @@ define <2 x i32> @test48_splat_vec(<2 x i32> %x) {
 
 define i32 @test49(i32 %x) {
 ; CHECK-LABEL: @test49(
-; CHECK-NEXT:    [[B:%.*]] = shl i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = shl i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = ashr exact i32 %x, 1
@@ -807,7 +807,7 @@ define i32 @test49(i32 %x) {
 
 define i32 @test49_nuw_nsw(i32 %x) {
 ; CHECK-LABEL: @test49_nuw_nsw(
-; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = ashr exact i32 %x, 1
@@ -819,7 +819,7 @@ define i32 @test49_nuw_nsw(i32 %x) {
 
 define <2 x i32> @test49_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test49_splat_vec(
-; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT:    [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
   %A = ashr exact <2 x i32> %x, <i32 1, i32 1>
@@ -831,7 +831,7 @@ define <2 x i32> @test49_splat_vec(<2 x i32> %x) {
 
 define i32 @test50(i32 %x) {
 ; CHECK-LABEL: @test50(
-; CHECK-NEXT:    [[B:%.*]] = ashr i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = ashr i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = shl nsw i32 %x, 1
@@ -844,7 +844,7 @@ define i32 @test50(i32 %x) {
 
 define <2 x i32> @test50_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test50_splat_vec(
-; CHECK-NEXT:    [[B:%.*]] = ashr exact <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT:    [[B:%.*]] = ashr exact <2 x i32> [[X:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
   %A = shl nsw <2 x i32> %x, <i32 1, i32 1>
@@ -856,7 +856,7 @@ define <2 x i32> @test50_splat_vec(<2 x i32> %x) {
 
 define i32 @test51(i32 %x) {
 ; CHECK-LABEL: @test51(
-; CHECK-NEXT:    [[B:%.*]] = lshr i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = lshr i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = shl nuw i32 %x, 1
@@ -869,7 +869,7 @@ define i32 @test51(i32 %x) {
 
 define <2 x i32> @test51_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test51_splat_vec(
-; CHECK-NEXT:    [[B:%.*]] = lshr exact <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT:    [[B:%.*]] = lshr exact <2 x i32> [[X:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
   %A = shl nuw <2 x i32> %x, <i32 1, i32 1>
@@ -882,7 +882,7 @@ define <2 x i32> @test51_splat_vec(<2 x i32> %x) {
 
 define i32 @test51_no_nuw(i32 %x) {
 ; CHECK-LABEL: @test51_no_nuw(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr exact i32 %x, 2
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr exact i32 [[X:%.*]], 2
 ; CHECK-NEXT:    [[B:%.*]] = and i32 [[TMP1]], 536870911
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
@@ -895,7 +895,7 @@ define i32 @test51_no_nuw(i32 %x) {
 
 define <2 x i32> @test51_no_nuw_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test51_no_nuw_splat_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    [[B:%.*]] = and <2 x i32> [[TMP1]], <i32 536870911, i32 536870911>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
@@ -908,7 +908,7 @@ define <2 x i32> @test51_no_nuw_splat_vec(<2 x i32> %x) {
 
 define i32 @test52(i32 %x) {
 ; CHECK-LABEL: @test52(
-; CHECK-NEXT:    [[B:%.*]] = shl nsw i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = shl nsw i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = shl nsw i32 %x, 3
@@ -920,7 +920,7 @@ define i32 @test52(i32 %x) {
 
 define <2 x i32> @test52_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test52_splat_vec(
-; CHECK-NEXT:    [[B:%.*]] = shl nsw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT:    [[B:%.*]] = shl nsw <2 x i32> [[X:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
   %A = shl nsw <2 x i32> %x, <i32 3, i32 3>
@@ -932,7 +932,7 @@ define <2 x i32> @test52_splat_vec(<2 x i32> %x) {
 
 define i32 @test53(i32 %x) {
 ; CHECK-LABEL: @test53(
-; CHECK-NEXT:    [[B:%.*]] = shl nuw i32 %x, 2
+; CHECK-NEXT:    [[B:%.*]] = shl nuw i32 [[X:%.*]], 2
 ; CHECK-NEXT:    ret i32 [[B]]
 ;
   %A = shl nuw i32 %x, 3
@@ -944,7 +944,7 @@ define i32 @test53(i32 %x) {
 
 define <2 x i32> @test53_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test53_splat_vec(
-; CHECK-NEXT:    [[B:%.*]] = shl nuw <2 x i32> %x, <i32 2, i32 2>
+; CHECK-NEXT:    [[B:%.*]] = shl nuw <2 x i32> [[X:%.*]], <i32 2, i32 2>
 ; CHECK-NEXT:    ret <2 x i32> [[B]]
 ;
   %A = shl nuw <2 x i32> %x, <i32 3, i32 3>
@@ -956,7 +956,7 @@ define <2 x i32> @test53_splat_vec(<2 x i32> %x) {
 
 define i8 @test53_no_nuw(i8 %x) {
 ; CHECK-LABEL: @test53_no_nuw(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i8 %x, 2
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i8 [[X:%.*]], 2
 ; CHECK-NEXT:    [[B:%.*]] = and i8 [[TMP1]], 124
 ; CHECK-NEXT:    ret i8 [[B]]
 ;
@@ -969,7 +969,7 @@ define i8 @test53_no_nuw(i8 %x) {
 
 define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) {
 ; CHECK-LABEL: @test53_no_nuw_splat_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i8> %x, <i8 2, i8 2>
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i8> [[X:%.*]], <i8 2, i8 2>
 ; CHECK-NEXT:    [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 124, i8 124>
 ; CHECK-NEXT:    ret <2 x i8> [[B]]
 ;
@@ -980,7 +980,7 @@ define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) {
 
 define i32 @test54(i32 %x) {
 ; CHECK-LABEL: @test54(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[TMP1]], 16
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
@@ -992,7 +992,7 @@ define i32 @test54(i32 %x) {
 
 define <2 x i32> @test54_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test54_splat_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> %x, <i32 3, i32 3>
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 3, i32 3>
 ; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[TMP1]], <i32 16, i32 16>
 ; CHECK-NEXT:    ret <2 x i32> [[AND]]
 ;
@@ -1004,7 +1004,7 @@ define <2 x i32> @test54_splat_vec(<2 x i32> %x) {
 
 define i32 @test55(i32 %x) {
 ; CHECK-LABEL: @test55(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 %x, 3
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[TMP1]], 8
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
@@ -1016,7 +1016,7 @@ define i32 @test55(i32 %x) {
 
 define i32 @test56(i32 %x) {
 ; CHECK-LABEL: @test56(
-; CHECK-NEXT:    [[SHR2:%.*]] = lshr i32 %x, 1
+; CHECK-NEXT:    [[SHR2:%.*]] = lshr i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[SHR2]], 4
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], 7
 ; CHECK-NEXT:    ret i32 [[OR]]
@@ -1029,8 +1029,8 @@ define i32 @test56(i32 %x) {
 
 define i32 @test57(i32 %x) {
 ; CHECK-LABEL: @test57(
-; CHECK-NEXT:    [[SHR1:%.*]] = lshr i32 %x, 1
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[SHR1]], 4
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[TMP1]], 4
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], 7
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
@@ -1042,7 +1042,7 @@ define i32 @test57(i32 %x) {
 
 define i32 @test58(i32 %x) {
 ; CHECK-LABEL: @test58(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 %x, 3
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[TMP1]], 1
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
@@ -1054,7 +1054,7 @@ define i32 @test58(i32 %x) {
 
 define <2 x i32> @test58_splat_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @test58_splat_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> %x, <i32 3, i32 3>
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 3, i32 3>
 ; CHECK-NEXT:    [[OR:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1>
 ; CHECK-NEXT:    ret <2 x i32> [[OR]]
 ;
@@ -1066,7 +1066,7 @@ define <2 x i32> @test58_splat_vec(<2 x i32> %x) {
 
 define i32 @test59(i32 %x) {
 ; CHECK-LABEL: @test59(
-; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 %x, 4
+; CHECK-NEXT:    [[SHR:%.*]] = ashr i32 [[X:%.*]], 4
 ; CHECK-NEXT:    [[SHL:%.*]] = shl nsw i32 [[SHR]], 1
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], 2
 ; CHECK-NEXT:    ret i32 [[OR]]
@@ -1080,7 +1080,7 @@ define i32 @test59(i32 %x) {
 ; propagate "exact" trait
 define i32 @test60(i32 %x) {
 ; CHECK-LABEL: @test60(
-; CHECK-NEXT:    [[SHL:%.*]] = ashr exact i32 %x, 3
+; CHECK-NEXT:    [[SHL:%.*]] = ashr exact i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], 1
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
@@ -1094,19 +1094,19 @@ define i32 @test60(i32 %x) {
 define void @test61(i128 %arg) {
 ; CHECK-LABEL: @test61(
 ; CHECK-NEXT:  bb:
-; CHECK-NEXT:    br i1 undef, label %bb1, label %bb12
+; CHECK-NEXT:    br i1 undef, label [[BB1:%.*]], label [[BB12:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    br label %bb2
+; CHECK-NEXT:    br label [[BB2:%.*]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    br i1 undef, label %bb3, label %bb7
+; CHECK-NEXT:    br i1 undef, label [[BB3:%.*]], label [[BB7:%.*]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    br label %bb8
+; CHECK-NEXT:    br label [[BB8:%.*]]
 ; CHECK:       bb7:
-; CHECK-NEXT:    br i1 undef, label %bb8, label %bb2
+; CHECK-NEXT:    br i1 undef, label [[BB8]], label [[BB2]]
 ; CHECK:       bb8:
-; CHECK-NEXT:    br i1 undef, label %bb11, label %bb12
+; CHECK-NEXT:    br i1 undef, label [[BB11:%.*]], label [[BB12]]
 ; CHECK:       bb11:
-; CHECK-NEXT:    br i1 undef, label %bb1, label %bb12
+; CHECK-NEXT:    br i1 undef, label [[BB1]], label [[BB12]]
 ; CHECK:       bb12:
 ; CHECK-NEXT:    ret void
 ;
@@ -1159,7 +1159,7 @@ define <4 x i32> @test62_splat_vector(<4 x i32> %a) {
 
 define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) {
 ; CHECK-LABEL: @test62_non_splat_vector(
-; CHECK-NEXT:    [[B:%.*]] = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2>
+; CHECK-NEXT:    [[B:%.*]] = ashr <4 x i32> [[A:%.*]], <i32 32, i32 0, i32 1, i32 2>
 ; CHECK-NEXT:    ret <4 x i32> [[B]]
 ;
   %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2>  ; shift all bits out
@@ -1168,7 +1168,7 @@ define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) {
 
 define <2 x i65> @test_63(<2 x i64> %t) {
 ; CHECK-LABEL: @test_63(
-; CHECK-NEXT:    [[A:%.*]] = zext <2 x i64> %t to <2 x i65>
+; CHECK-NEXT:    [[A:%.*]] = zext <2 x i64> [[T:%.*]] to <2 x i65>
 ; CHECK-NEXT:    [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33>
 ; CHECK-NEXT:    [[B:%.*]] = ashr exact <2 x i65> [[SEXT]], <i65 33, i65 33>
 ; CHECK-NEXT:    ret <2 x i65> [[B]]
@@ -1294,7 +1294,7 @@ define i64 @shl_zext_mul_extra_use2(i32 %t) {
 
 define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) {
 ; CHECK-LABEL: @ashr_demanded_bits_splat(
-; CHECK-NEXT:    [[SHR:%.*]] = ashr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT:    [[SHR:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7>
 ; CHECK-NEXT:    ret <2 x i8> [[SHR]]
 ;
   %and = and <2 x i8> %x, <i8 128, i8 128>
@@ -1304,7 +1304,7 @@ define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) {
 
 define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) {
 ; CHECK-LABEL: @lshr_demanded_bits_splat(
-; CHECK-NEXT:    [[SHR:%.*]] = lshr <2 x i8> %x, <i8 7, i8 7>
+; CHECK-NEXT:    [[SHR:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 7, i8 7>
 ; CHECK-NEXT:    ret <2 x i8> [[SHR]]
 ;
   %and = and <2 x i8> %x, <i8 128, i8 128>