From ae6f1e07fcc356f0c4a8615d74814c6f8aadbd72 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 8 Jan 2019 01:13:20 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Disallow VGPR->SCC copies This fixes using scalar adds when only the carry in is a VGPR using greedy regbankselect. llvm-svn: 350593 --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 ++++++++-- .../CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir | 6 ++++-- .../CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir | 6 ++++-- .../CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir | 6 ++++-- .../CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir | 6 ++++-- 5 files changed, 24 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index e40961e96e1b..9d576e621600 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -74,13 +74,19 @@ unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const { if (Dst.getID() == AMDGPU::SGPRRegBankID && - Src.getID() == AMDGPU::VGPRRegBankID) + Src.getID() == AMDGPU::VGPRRegBankID) { + // For boolean values, we can do a v_cmp to "copy" a VGPR to VCC. + if (Size == 1) + return 1; + return std::numeric_limits::max(); + } // SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by // the valu. if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID && - Src.getID() == AMDGPU::SGPRRegBankID) + (Src.getID() == AMDGPU::SGPRRegBankID || + Src.getID() == AMDGPU::VGPRRegBankID)) return std::numeric_limits::max(); return RegisterBankInfo::copyCost(Dst, Src, Size); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir index e35ee8f15404..af72caa9acf0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir @@ -84,8 +84,10 @@ body: | ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1) - ; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1) + ; GREEDY: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir index dcbe32f7eca6..d71da505e110 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir @@ -84,8 +84,10 @@ body: | ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1) - ; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1) + ; GREEDY: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir index 76b7a85f381c..0f31ca094242 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir @@ -83,8 +83,10 @@ body: | ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1) - ; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[COPY3]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1) + ; GREEDY: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s1) = G_UADDE [[COPY3]], [[COPY4]], [[COPY5]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir index 819ea8e68b5a..f13de31fc47d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir @@ -84,8 +84,10 @@ body: | ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:scc(s1) = COPY [[TRUNC]](s1) - ; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[COPY3]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY5:%[0-9]+]]:sgpr(s1) = COPY [[TRUNC]](s1) + ; GREEDY: [[USUBE:%[0-9]+]]:vgpr(s32), [[USUBE1:%[0-9]+]]:sgpr(s1) = G_USUBE [[COPY3]], [[COPY4]], [[COPY5]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $vgpr0