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Teach the MBlaze disassembler to disassemble special purpose registers. 

llvm-svn: 122269
This commit is contained in:
Wesley Peck 2010-12-20 21:18:04 +00:00
parent 55184ddd35
commit ae58e7b179
3 changed files with 89 additions and 10 deletions
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7
llvm/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
View File

@ -69,8 +69,7 @@ static unsigned getRB(uint32_t insn) {
} }
static int64_t getRS(uint32_t insn) { static int64_t getRS(uint32_t insn) {
int16_t val = (insn & 0x3FFF); return MBlazeRegisterInfo::getSpecialRegisterFromNumbering(insn&0x3FFF);
return val;
} }
static int64_t getIMM(uint32_t insn) { static int64_t getIMM(uint32_t insn) {
@ -606,12 +605,12 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
case MBlazeII::FRCS: case MBlazeII::FRCS:
instr.addOperand(MCOperand::CreateReg(getRD(insn))); instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateImm(getRS(insn))); instr.addOperand(MCOperand::CreateReg(getRS(insn)));
break; break;
case MBlazeII::FCRCS: case MBlazeII::FCRCS:
instr.addOperand(MCOperand::CreateReg(getRS(insn)));
instr.addOperand(MCOperand::CreateReg(getRA(insn))); instr.addOperand(MCOperand::CreateReg(getRA(insn)));
instr.addOperand(MCOperand::CreateImm(getRS(insn)));
break; break;
case MBlazeII::FCRCX: case MBlazeII::FCRCX:

12
llvm/lib/Target/MBlaze/MBlazeInstrInfo.td
View File

@ -599,11 +599,15 @@ let isCodeGenOnly=1 in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Misc. instructions // Misc. instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src), let Form=FRCS in {
"mfs $dst, $src", [], IIAlu>; def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src),
"mfs $dst, $src", [], IIAlu>;
}
def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src), let Form=FCRCS in {
"mts $dst, $src", [], IIAlu>; def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src),
"mts $dst, $src", [], IIAlu>;
}
def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set), def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set),
"msrset $dst, $set", [], IIAlu>; "msrset $dst, $set", [], IIAlu>;

80
llvm/test/MC/Disassembler/MBlaze/mblaze_special.txt
View File

@ -4,7 +4,7 @@
# Special instructions # Special instructions
################################################################################ ################################################################################
# CHECK: mfs r0, 0 # CHECK: mfs r0, rpc
0x94 0x00 0x80 0x00 0x94 0x00 0x80 0x00
# CHECK: msrclr r0, 0 # CHECK: msrclr r0, 0
@ -13,7 +13,7 @@
# CHECK: msrset r0, 0 # CHECK: msrset r0, 0
0x94 0x10 0x00 0x00 0x94 0x10 0x00 0x00
# CHECK: mts 0, r0 # CHECK: mts rpc, r0
0x94 0x00 0xc0 0x00 0x94 0x00 0xc0 0x00
# CHECK: wdc r0, r1 # CHECK: wdc r0, r1
@ -27,3 +27,79 @@
# CHECK: wic r0, r1 # CHECK: wic r0, r1
0x90 0x00 0x08 0x68 0x90 0x00 0x08 0x68
################################################################################
# Special registers
################################################################################
# CHECK: mfs r1, rpc
0x94 0x20 0x80 0x00
# CHECK: mfs r1, rmsr
0x94 0x20 0x80 0x01
# CHECK: mfs r1, rear
0x94 0x20 0x80 0x03
# CHECK: mfs r1, resr
0x94 0x20 0x80 0x05
# CHECK: mfs r1, rfsr
0x94 0x20 0x80 0x07
# CHECK: mfs r1, rbtr
0x94 0x20 0x80 0x0b
# CHECK: mfs r1, redr
0x94 0x20 0x80 0x0d
# CHECK: mfs r1, rpid
0x94 0x20 0x90 0x00
# CHECK: mfs r1, rzpr
0x94 0x20 0x90 0x01
# CHECK: mfs r1, rtlbx
0x94 0x20 0x90 0x02
# CHECK: mfs r1, rtlbhi
0x94 0x20 0x90 0x04
# CHECK: mfs r1, rtlblo
0x94 0x20 0x90 0x03
# CHECK: mfs r1, rpvr0
0x94 0x20 0xa0 0x00
# CHECK: mfs r1, rpvr1
0x94 0x20 0xa0 0x01
# CHECK: mfs r1, rpvr2
0x94 0x20 0xa0 0x02
# CHECK: mfs r1, rpvr3
0x94 0x20 0xa0 0x03
# CHECK: mfs r1, rpvr4
0x94 0x20 0xa0 0x04
# CHECK: mfs r1, rpvr5
0x94 0x20 0xa0 0x05
# CHECK: mfs r1, rpvr6
0x94 0x20 0xa0 0x06
# CHECK: mfs r1, rpvr7
0x94 0x20 0xa0 0x07
# CHECK: mfs r1, rpvr8
0x94 0x20 0xa0 0x08
# CHECK: mfs r1, rpvr9
0x94 0x20 0xa0 0x09
# CHECK: mfs r1, rpvr10
0x94 0x20 0xa0 0x0a
# CHECK: mfs r1, rpvr11
0x94 0x20 0xa0 0x0b