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MC: Tidy up comments and clean up formatting a bit. NFC. 

llvm-svn: 236368
This commit is contained in:
Jim Grosbach 2015-05-02 00:44:14 +00:00
parent bfe3a9c318
commit ae4c2649dc
28 changed files with 566 additions and 648 deletions
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4
llvm/include/llvm/MC/MCAsmBackend.h
View File

@ -61,7 +61,7 @@ public:
/// region directives will be ignored.
bool hasDataInCodeSupport() const { return HasDataInCodeSupport; }
/// @name Target Fixup Interfaces
/// \name Target Fixup Interfaces
/// @{
/// Get the number of target specific fixup kinds.
@ -87,7 +87,7 @@ public:
/// @}
/// @name Target Relaxation Interfaces
/// \name Target Relaxation Interfaces
/// @{
/// Check whether the given instruction may need relaxation.

8
llvm/include/llvm/MC/MCAsmLayout.h
View File

@ -66,7 +66,7 @@ public:
/// been initialized.
void layoutFragment(MCFragment *Fragment);
/// @name Section Access (in layout order)
/// \name Section Access (in layout order)
/// @{
llvm::SmallVectorImpl<MCSectionData*> &getSectionOrder() {
@ -77,14 +77,14 @@ public:
}
/// @}
/// @name Fragment Layout Data
/// \name Fragment Layout Data
/// @{
/// \brief Get the offset of the given fragment inside its containing section.
uint64_t getFragmentOffset(const MCFragment *F) const;
/// @}
/// @name Utility Functions
/// \name Utility Functions
/// @{
/// \brief Get the address space size of the given section, as it effects
@ -98,7 +98,7 @@ public:
/// \brief Get the offset of the given symbol, as computed in the current
/// layout.
/// \result True on success.
/// \return True on success.
bool getSymbolOffset(const MCSymbolData *SD, uint64_t &Val) const;
/// \brief Variant that reports a fatal error if the offset is not computable.

36
llvm/include/llvm/MC/MCAssembler.h
View File

@ -73,7 +73,7 @@ private:
/// symbol.
MCSymbolData *Atom;
/// @name Assembler Backend Data
/// \name Assembler Backend Data
/// @{
//
// FIXME: This could all be kept private to the assembler implementation.
@ -367,7 +367,7 @@ public:
: MCFragment(FT_Align, SD), Alignment(Alignment), Value(Value),
ValueSize(ValueSize), MaxBytesToEmit(MaxBytesToEmit), EmitNops(false) {}
/// @name Accessors
/// \name Accessors
/// @{
unsigned getAlignment() const { return Alignment; }
@ -410,7 +410,7 @@ public:
"Fill size must be a multiple of the value size!");
}
/// @name Accessors
/// \name Accessors
/// @{
int64_t getValue() const { return Value; }
@ -439,7 +439,7 @@ public:
MCOrgFragment(const MCExpr &Offset, int8_t Value, MCSectionData *SD = nullptr)
: MCFragment(FT_Org, SD), Offset(&Offset), Value(Value) {}
/// @name Accessors
/// \name Accessors
/// @{
const MCExpr &getOffset() const { return *Offset; }
@ -469,7 +469,7 @@ public:
: MCFragment(FT_LEB, SD),
Value(&Value_), IsSigned(IsSigned_) { Contents.push_back(0); }
/// @name Accessors
/// \name Accessors
/// @{
const MCExpr &getValue() const { return *Value; }
@ -506,7 +506,7 @@ public:
Contents.push_back(0);
}
/// @name Accessors
/// \name Accessors
/// @{
int64_t getLineDelta() const { return LineDelta; }
@ -538,7 +538,7 @@ public:
Contents.push_back(0);
}
/// @name Accessors
/// \name Accessors
/// @{
const MCExpr &getAddrDelta() const { return *AddrDelta; }
@ -600,7 +600,7 @@ private:
/// yet.
bool BundleGroupBeforeFirstInst;
/// @name Assembler Backend Data
/// \name Assembler Backend Data
/// @{
//
// FIXME: This could all be kept private to the assembler implementation.
@ -634,7 +634,7 @@ public:
unsigned getLayoutOrder() const { return LayoutOrder; }
void setLayoutOrder(unsigned Value) { LayoutOrder = Value; }
/// @name Fragment Access
/// \name Fragment Access
/// @{
const FragmentListType &getFragmentList() const { return Fragments; }
@ -721,7 +721,7 @@ public:
MCSymbolData(const MCSymbol &Symbol, MCFragment *Fragment, uint64_t Offset,
MCAssembler *A = nullptr);
/// @name Accessors
/// \name Accessors
/// @{
const MCSymbol &getSymbol() const { return *Symbol; }
@ -739,7 +739,7 @@ public:
}
/// @}
/// @name Symbol Attributes
/// \name Symbol Attributes
/// @{
bool isExternal() const { return Fragment.getInt() & 1; }
@ -1077,7 +1077,7 @@ public:
BundleAlignSize = Size;
}
/// @name Section List Access
/// \name Section List Access
/// @{
const SectionDataListType &getSectionList() const { return Sections; }
@ -1092,7 +1092,7 @@ public:
size_t size() const { return Sections.size(); }
/// @}
/// @name Symbol List Access
/// \name Symbol List Access
/// @{
const SymbolDataListType &getSymbolList() const { return Symbols; }
@ -1110,7 +1110,7 @@ public:
size_t symbol_size() const { return Symbols.size(); }
/// @}
/// @name Indirect Symbol List Access
/// \name Indirect Symbol List Access
/// @{
// FIXME: This is a total hack, this should not be here. Once things are
@ -1137,7 +1137,7 @@ public:
size_t indirect_symbol_size() const { return IndirectSymbols.size(); }
/// @}
/// @name Linker Option List Access
/// \name Linker Option List Access
/// @{
std::vector<std::vector<std::string> > &getLinkerOptions() {
@ -1145,7 +1145,7 @@ public:
}
/// @}
/// @name Data Region List Access
/// \name Data Region List Access
/// @{
// FIXME: This is a total hack, this should not be here. Once things are
@ -1172,7 +1172,7 @@ public:
size_t data_region_size() const { return DataRegions.size(); }
/// @}
/// @name Data Region List Access
/// \name Data Region List Access
/// @{
// FIXME: This is a total hack, this should not be here. Once things are
@ -1185,7 +1185,7 @@ public:
return const_cast<MCAssembler *>(this)->getLOHContainer();
}
/// @}
/// @name Backend Data Access
/// \name Backend Data Access
/// @{
MCSectionData &getSectionData(const MCSection &Section) const {

48
llvm/include/llvm/MC/MCContext.h
View File

@ -225,7 +225,7 @@ namespace llvm {
void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; }
/// @name Module Lifetime Management
/// \name Module Lifetime Management
/// @{
/// reset - return object to right after construction state to prepare
@ -234,7 +234,7 @@ namespace llvm {
/// @}
/// @name Symbol Management
/// \name Symbol Management
/// @{
/// Create and return a new linker temporary symbol with a unique but
@ -255,10 +255,10 @@ namespace llvm {
/// for "1b" or 1f" references).
MCSymbol *GetDirectionalLocalSymbol(unsigned LocalLabelVal, bool Before);
/// Lookup the symbol inside with the specified @p Name. If it exists,
/// Lookup the symbol inside with the specified \p Name. If it exists,
/// return it. If not, create a forward reference and return it.
///
/// @param Name - The symbol name, which must be unique across all symbols.
/// \param Name - The symbol name, which must be unique across all symbols.
MCSymbol *GetOrCreateSymbol(const Twine &Name);
MCSymbol *getOrCreateSectionSymbol(const MCSectionELF &Section);
@ -266,7 +266,7 @@ namespace llvm {
/// Gets a symbol that will be defined to the final stack offset of a local
/// variable after codegen.
///
/// @param Idx - The index of a local variable passed to @llvm.frameescape.
/// \param Idx - The index of a local variable passed to @llvm.frameescape.
MCSymbol *getOrCreateFrameAllocSymbol(StringRef FuncName, unsigned Idx);
MCSymbol *getOrCreateParentFrameOffsetSymbol(StringRef FuncName);
@ -284,7 +284,7 @@ namespace llvm {
/// @}
/// @name Section Management
/// \name Section Management
/// @{
/// Return the MCSection for the specified mach-o section. This requires
@ -376,7 +376,7 @@ namespace llvm {
/// @}
/// @name Dwarf Management
/// \name Dwarf Management
/// @{
/// \brief Get the compilation directory for DW_AT_comp_dir
@ -523,33 +523,33 @@ namespace llvm {
// operator new and delete aren't allowed inside namespaces.
// The throw specifications are mandated by the standard.
/// @brief Placement new for using the MCContext's allocator.
/// \brief Placement new for using the MCContext's allocator.
///
/// This placement form of operator new uses the MCContext's allocator for
/// obtaining memory. It is a non-throwing new, which means that it returns
/// null on error. (If that is what the allocator does. The current does, so if
/// this ever changes, this operator will have to be changed, too.)
/// Usage looks like this (assuming there's an MCContext 'Context' in scope):
/// @code
/// \code
/// // Default alignment (16)
/// IntegerLiteral *Ex = new (Context) IntegerLiteral(arguments);
/// // Specific alignment
/// IntegerLiteral *Ex2 = new (Context, 8) IntegerLiteral(arguments);
/// @endcode
/// \endcode
/// Please note that you cannot use delete on the pointer; it must be
/// deallocated using an explicit destructor call followed by
/// @c Context.Deallocate(Ptr).
/// \c Context.Deallocate(Ptr).
///
/// @param Bytes The number of bytes to allocate. Calculated by the compiler.
/// @param C The MCContext that provides the allocator.
/// @param Alignment The alignment of the allocated memory (if the underlying
/// \param Bytes The number of bytes to allocate. Calculated by the compiler.
/// \param C The MCContext that provides the allocator.
/// \param Alignment The alignment of the allocated memory (if the underlying
/// allocator supports it).
/// @return The allocated memory. Could be NULL.
/// \return The allocated memory. Could be NULL.
inline void *operator new(size_t Bytes, llvm::MCContext &C,
size_t Alignment = 16) throw () {
return C.Allocate(Bytes, Alignment);
}
/// @brief Placement delete companion to the new above.
/// \brief Placement delete companion to the new above.
///
/// This operator is just a companion to the new above. There is no way of
/// invoking it directly; see the new operator for more details. This operator
@ -564,27 +564,27 @@ inline void operator delete(void *Ptr, llvm::MCContext &C, size_t)
/// obtaining memory. It is a non-throwing new[], which means that it returns
/// null on error.
/// Usage looks like this (assuming there's an MCContext 'Context' in scope):
/// @code
/// \code
/// // Default alignment (16)
/// char *data = new (Context) char[10];
/// // Specific alignment
/// char *data = new (Context, 8) char[10];
/// @endcode
/// \endcode
/// Please note that you cannot use delete on the pointer; it must be
/// deallocated using an explicit destructor call followed by
/// @c Context.Deallocate(Ptr).
/// \c Context.Deallocate(Ptr).
///
/// @param Bytes The number of bytes to allocate. Calculated by the compiler.
/// @param C The MCContext that provides the allocator.
/// @param Alignment The alignment of the allocated memory (if the underlying
/// \param Bytes The number of bytes to allocate. Calculated by the compiler.
/// \param C The MCContext that provides the allocator.
/// \param Alignment The alignment of the allocated memory (if the underlying
/// allocator supports it).
/// @return The allocated memory. Could be NULL.
/// \return The allocated memory. Could be NULL.
inline void *operator new[](size_t Bytes, llvm::MCContext& C,
size_t Alignment = 16) throw () {
return C.Allocate(Bytes, Alignment);
}
/// @brief Placement delete[] companion to the new[] above.
/// \brief Placement delete[] companion to the new[] above.
///
/// This operator is just a companion to the new[] above. There is no way of
/// invoking it directly; see the new[] operator for more details. This operator

12
llvm/include/llvm/MC/MCDisassembler.h
View File

@ -61,16 +61,16 @@ public:
/// Returns the disassembly of a single instruction.
///
/// @param Instr - An MCInst to populate with the contents of the
/// \param Instr - An MCInst to populate with the contents of the
/// instruction.
/// @param Size - A value to populate with the size of the instruction, or
/// \param Size - A value to populate with the size of the instruction, or
/// the number of bytes consumed while attempting to decode
/// an invalid instruction.
/// @param Address - The address, in the memory space of region, of the first
/// \param Address - The address, in the memory space of region, of the first
/// byte of the instruction.
/// @param VStream - The stream to print warnings and diagnostic messages on.
/// @param CStream - The stream to print comments and annotations on.
/// @return - MCDisassembler::Success if the instruction is valid,
/// \param VStream - The stream to print warnings and diagnostic messages on.
/// \param CStream - The stream to print comments and annotations on.
/// \return - MCDisassembler::Success if the instruction is valid,
/// MCDisassembler::SoftFail if the instruction was
/// disassemblable but invalid,
/// MCDisassembler::Fail if the instruction was invalid.

47
llvm/include/llvm/MC/MCDwarf.h
View File

@ -37,34 +37,29 @@ class MCSymbol;
class SourceMgr;
class SMLoc;
/// MCDwarfFile - Instances of this class represent the name of the dwarf
/// \brief Instances of this class represent the name of the dwarf
/// .file directive and its associated dwarf file number in the MC file,
/// and MCDwarfFile's are created and uniqued by the MCContext class where
/// the file number for each is its index into the vector of DwarfFiles (note
/// index 0 is not used and not a valid dwarf file number).
struct MCDwarfFile {
// Name - the base name of the file without its directory path.
// \brief The base name of the file without its directory path.
// The StringRef references memory allocated in the MCContext.
std::string Name;
// DirIndex - the index into the list of directory names for this file name.
// \brief The index into the list of directory names for this file name.
unsigned DirIndex;
};
/// MCDwarfLoc - Instances of this class represent the information from a
/// \brief Instances of this class represent the information from a
/// dwarf .loc directive.
class MCDwarfLoc {
// FileNum - the file number.
unsigned FileNum;
// Line - the line number.
unsigned Line;
// Column - the column position.
unsigned Column;
// Flags (see #define's below)
unsigned Flags;
// Isa
unsigned Isa;
// Discriminator
unsigned Discriminator;
// Flag that indicates the initial value of the is_stmt_start flag.
@ -87,46 +82,46 @@ private: // MCContext manages these
// for an MCDwarfLoc object.
public:
/// getFileNum - Get the FileNum of this MCDwarfLoc.
/// \brief Get the FileNum of this MCDwarfLoc.
unsigned getFileNum() const { return FileNum; }
/// getLine - Get the Line of this MCDwarfLoc.
/// \brief Get the Line of this MCDwarfLoc.
unsigned getLine() const { return Line; }
/// getColumn - Get the Column of this MCDwarfLoc.
/// \brief Get the Column of this MCDwarfLoc.
unsigned getColumn() const { return Column; }
/// getFlags - Get the Flags of this MCDwarfLoc.
/// \brief Get the Flags of this MCDwarfLoc.
unsigned getFlags() const { return Flags; }
/// getIsa - Get the Isa of this MCDwarfLoc.
/// \brief Get the Isa of this MCDwarfLoc.
unsigned getIsa() const { return Isa; }
/// getDiscriminator - Get the Discriminator of this MCDwarfLoc.
/// \brief Get the Discriminator of this MCDwarfLoc.
unsigned getDiscriminator() const { return Discriminator; }
/// setFileNum - Set the FileNum of this MCDwarfLoc.
/// \brief Set the FileNum of this MCDwarfLoc.
void setFileNum(unsigned fileNum) { FileNum = fileNum; }
/// setLine - Set the Line of this MCDwarfLoc.
/// \brief Set the Line of this MCDwarfLoc.
void setLine(unsigned line) { Line = line; }
/// setColumn - Set the Column of this MCDwarfLoc.
/// \brief Set the Column of this MCDwarfLoc.
void setColumn(unsigned column) { Column = column; }
/// setFlags - Set the Flags of this MCDwarfLoc.
/// \brief Set the Flags of this MCDwarfLoc.
void setFlags(unsigned flags) { Flags = flags; }
/// setIsa - Set the Isa of this MCDwarfLoc.
/// \brief Set the Isa of this MCDwarfLoc.
void setIsa(unsigned isa) { Isa = isa; }
/// setDiscriminator - Set the Discriminator of this MCDwarfLoc.
/// \brief Set the Discriminator of this MCDwarfLoc.
void setDiscriminator(unsigned discriminator) {
Discriminator = discriminator;
}
};
/// MCLineEntry - Instances of this class represent the line information for
/// \brief Instances of this class represent the line information for
/// the dwarf line table entries. Which is created after a machine
/// instruction is assembled and uses an address from a temporary label
/// created at the current address in the current section and the info from
@ -151,13 +146,13 @@ public:
static void Make(MCObjectStreamer *MCOS, const MCSection *Section);
};
/// MCLineSection - Instances of this class represent the line information
/// for a compile unit where machine instructions have been assembled after seeing
/// .loc directives. This is the information used to build the dwarf line
/// \brief Instances of this class represent the line information for a compile
/// unit where machine instructions have been assembled after seeing .loc
/// directives. This is the information used to build the dwarf line
/// table for a section.
class MCLineSection {
public:
// addLineEntry - adds an entry to this MCLineSection's line entries
// \brief Add an entry to this MCLineSection's line entries.
void addLineEntry(const MCLineEntry &LineEntry, const MCSection *Sec) {
MCLineDivisions[Sec].push_back(LineEntry);
}

2
llvm/include/llvm/MC/MCELFObjectWriter.h
View File

@ -76,7 +76,7 @@ public:
virtual void sortRelocs(const MCAssembler &Asm,
std::vector<ELFRelocationEntry> &Relocs);
/// @name Accessors
/// \name Accessors
/// @{
uint8_t getOSABI() const { return OSABI; }
uint16_t getEMachine() const { return EMachine; }

2
llvm/include/llvm/MC/MCELFStreamer.h
View File

@ -44,7 +44,7 @@ public:
MCObjectStreamer::reset();
}
/// @name MCStreamer Interface
/// \name MCStreamer Interface
/// @{
void InitSections(bool NoExecStack) override;

73
llvm/include/llvm/MC/MCExpr.h
View File

@ -29,7 +29,7 @@ class raw_ostream;
class StringRef;
typedef DenseMap<const MCSectionData*, uint64_t> SectionAddrMap;
/// MCExpr - Base class for the full range of assembler expressions which are
/// \brief Base class for the full range of assembler expressions which are
/// needed for parsing.
class MCExpr {
public:
@ -64,29 +64,29 @@ protected:
const SectionAddrMap *Addrs, bool InSet) const;
public:
/// @name Accessors
/// \name Accessors
/// @{
ExprKind getKind() const { return Kind; }
/// @}
/// @name Utility Methods
/// \name Utility Methods
/// @{
void print(raw_ostream &OS) const;
void dump() const;
/// @}
/// @name Expression Evaluation
/// \name Expression Evaluation
/// @{
/// EvaluateAsAbsolute - Try to evaluate the expression to an absolute value.
/// \brief Try to evaluate the expression to an absolute value.
///
/// @param Res - The absolute value, if evaluation succeeds.
/// @param Layout - The assembler layout object to use for evaluating symbol
/// \param Res - The absolute value, if evaluation succeeds.
/// \param Layout - The assembler layout object to use for evaluating symbol
/// values. If not given, then only non-symbolic expressions will be
/// evaluated.
/// @result - True on success.
/// \return - True on success.
bool EvaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout,
const SectionAddrMap &Addrs) const;
bool EvaluateAsAbsolute(int64_t &Res) const;
@ -95,13 +95,13 @@ public:
bool evaluateKnownAbsolute(int64_t &Res, const MCAsmLayout &Layout) const;
/// EvaluateAsRelocatable - Try to evaluate the expression to a relocatable
/// value, i.e. an expression of the fixed form (a - b + constant).
/// \brief Try to evaluate the expression to a relocatable value, i.e. an
/// expression of the fixed form (a - b + constant).
///
/// @param Res - The relocatable value, if evaluation succeeds.
/// @param Layout - The assembler layout object to use for evaluating values.
/// @param Fixup - The Fixup object if available.
/// @result - True on success.
/// \param Res - The relocatable value, if evaluation succeeds.
/// \param Layout - The assembler layout object to use for evaluating values.
/// \param Fixup - The Fixup object if available.
/// \return - True on success.
bool EvaluateAsRelocatable(MCValue &Res, const MCAsmLayout *Layout,
const MCFixup *Fixup) const;
@ -112,8 +112,8 @@ public:
/// use is for when relocations are not available, like the .size directive.
bool evaluateAsValue(MCValue &Res, const MCAsmLayout &Layout) const;
/// FindAssociatedSection - Find the "associated section" for this expression,
/// which is currently defined as the absolute section for constants, or
/// \brief Find the "associated section" for this expression, which is
/// currently defined as the absolute section for constants, or
/// otherwise the section associated with the first defined symbol in the
/// expression.
const MCSection *FindAssociatedSection() const;
@ -126,7 +126,7 @@ inline raw_ostream &operator<<(raw_ostream &OS, const MCExpr &E) {
return OS;
}
//// MCConstantExpr - Represent a constant integer expression.
//// \brief Represent a constant integer expression.
class MCConstantExpr : public MCExpr {
int64_t Value;
@ -134,13 +134,13 @@ class MCConstantExpr : public MCExpr {
: MCExpr(MCExpr::Constant), Value(Value) {}
public:
/// @name Construction
/// \name Construction
/// @{
static const MCConstantExpr *Create(int64_t Value, MCContext &Ctx);
/// @}
/// @name Accessors
/// \name Accessors
/// @{
int64_t getValue() const { return Value; }
@ -152,8 +152,7 @@ public:
}
};
/// MCSymbolRefExpr - Represent a reference to a symbol from inside an
/// expression.
/// \brief Represent a reference to a symbol from inside an expression.
///
/// A symbol reference in an expression may be a use of a label, a use of an
/// assembler variable (defined constant), or constitute an implicit definition
@ -311,7 +310,7 @@ private:
const MCAsmInfo *MAI);
public:
/// @name Construction
/// \name Construction
/// @{
static const MCSymbolRefExpr *Create(const MCSymbol *Symbol, MCContext &Ctx) {
@ -324,7 +323,7 @@ public:
MCContext &Ctx);
/// @}
/// @name Accessors
/// \name Accessors
/// @{
const MCSymbol &getSymbol() const { return *Symbol; }
@ -336,7 +335,7 @@ public:
bool hasSubsectionsViaSymbols() const { return HasSubsectionsViaSymbols; }
/// @}
/// @name Static Utility Functions
/// \name Static Utility Functions
/// @{
static StringRef getVariantKindName(VariantKind Kind);
@ -350,7 +349,7 @@ public:
}
};
/// MCUnaryExpr - Unary assembler expressions.
/// \brief Unary assembler expressions.
class MCUnaryExpr : public MCExpr {
public:
enum Opcode {
@ -368,7 +367,7 @@ private:
: MCExpr(MCExpr::Unary), Op(Op), Expr(Expr) {}
public:
/// @name Construction
/// \name Construction
/// @{
static const MCUnaryExpr *Create(Opcode Op, const MCExpr *Expr,
@ -387,13 +386,13 @@ public:
}
/// @}
/// @name Accessors
/// \name Accessors
/// @{
/// getOpcode - Get the kind of this unary expression.
/// \brief Get the kind of this unary expression.
Opcode getOpcode() const { return Op; }
/// getSubExpr - Get the child of this unary expression.
/// \brief Get the child of this unary expression.
const MCExpr *getSubExpr() const { return Expr; }
/// @}
@ -403,7 +402,7 @@ public:
}
};
/// MCBinaryExpr - Binary assembler expressions.
/// \brief Binary assembler expressions.
class MCBinaryExpr : public MCExpr {
public:
enum Opcode {
@ -440,7 +439,7 @@ private:
: MCExpr(MCExpr::Binary), Op(Op), LHS(LHS), RHS(RHS) {}
public:
/// @name Construction
/// \name Construction
/// @{
static const MCBinaryExpr *Create(Opcode Op, const MCExpr *LHS,
@ -523,16 +522,16 @@ public:
}
/// @}
/// @name Accessors
/// \name Accessors
/// @{
/// getOpcode - Get the kind of this binary expression.
/// \brief Get the kind of this binary expression.
Opcode getOpcode() const { return Op; }
/// getLHS - Get the left-hand side expression of the binary operator.
/// \brief Get the left-hand side expression of the binary operator.
const MCExpr *getLHS() const { return LHS; }
/// getRHS - Get the right-hand side expression of the binary operator.
/// \brief Get the right-hand side expression of the binary operator.
const MCExpr *getRHS() const { return RHS; }
/// @}
@ -542,8 +541,8 @@ public:
}
};
/// MCTargetExpr - This is an extension point for target-specific MCExpr
/// subclasses to implement.
/// \brief This is an extension point for target-specific MCExpr subclasses to
/// implement.
///
/// NOTE: All subclasses are required to have trivial destructors because
/// MCExprs are bump pointer allocated and not destructed.

8
llvm/include/llvm/MC/MCFixup.h
View File

@ -19,7 +19,7 @@
namespace llvm {
class MCExpr;
/// MCFixupKind - Extensible enumeration to represent the type of a fixup.
/// \brief Extensible enumeration to represent the type of a fixup.
enum MCFixupKind {
FK_Data_1 = 0, ///< A one-byte fixup.
FK_Data_2, ///< A two-byte fixup.
@ -45,7 +45,7 @@ enum MCFixupKind {
MaxTargetFixupKind = (1 << 8)
};
/// MCFixup - Encode information on a single operation to perform on a byte
/// \brief Encode information on a single operation to perform on a byte
/// sequence (e.g., an encoded instruction) which requires assemble- or run-
/// time patching.
///
@ -93,8 +93,8 @@ public:
const MCExpr *getValue() const { return Value; }
/// getKindForSize - Return the generic fixup kind for a value with the given
/// size. It is an error to pass an unsupported size.
/// \brief Return the generic fixup kind for a value with the given size. It
/// is an error to pass an unsupported size.
static MCFixupKind getKindForSize(unsigned Size, bool isPCRel) {
switch (Size) {
default: llvm_unreachable("Invalid generic fixup size!");

2
llvm/include/llvm/MC/MCFixupKindInfo.h
View File

@ -12,7 +12,7 @@
namespace llvm {
/// MCFixupKindInfo - Target independent information on a fixup kind.
/// \brief Target independent information on a fixup kind.
struct MCFixupKindInfo {
enum FixupKindFlags {
/// Is this fixup kind PCrelative? This is used by the assembler backend to

8
llvm/include/llvm/MC/MCInst.h
View File

@ -28,7 +28,7 @@ class MCInstPrinter;
class MCExpr;
class MCInst;
/// MCOperand - Instances of this class represent operands of the MCInst class.
/// \brief Instances of this class represent operands of the MCInst class.
/// This is a simple discriminated union.
class MCOperand {
enum MachineOperandType : unsigned char {
@ -59,13 +59,13 @@ public:
bool isExpr() const { return Kind == kExpr; }
bool isInst() const { return Kind == kInst; }
/// getReg - Returns the register number.
/// \brief Returns the register number.
unsigned getReg() const {
assert(isReg() && "This is not a register operand!");
return RegVal;
}
/// setReg - Set the register number.
/// \brief Set the register number.
void setReg(unsigned Reg) {
assert(isReg() && "This is not a register operand!");
RegVal = Reg;
@ -145,7 +145,7 @@ public:
template <> struct isPodLike<MCOperand> { static const bool value = true; };
/// MCInst - Instances of this class represent a single low-level machine
/// \brief Instances of this class represent a single low-level machine
/// instruction.
class MCInst {
unsigned Opcode;

21
llvm/include/llvm/MC/MCInstPrinter.h
View File

@ -29,13 +29,13 @@ namespace HexStyle {
};
}
/// MCInstPrinter - This is an instance of a target assembly language printer
/// that converts an MCInst to valid target assembly syntax.
/// \brief This is an instance of a target assembly language printer that
/// converts an MCInst to valid target assembly syntax.
class MCInstPrinter {
protected:
/// CommentStream - a stream that comments can be emitted to if desired.
/// Each comment must end with a newline. This will be null if verbose
/// assembly emission is disable.
/// \brief A stream that comments can be emitted to if desired. Each comment
/// must end with a newline. This will be null if verbose assembly emission
/// is disable.
raw_ostream *CommentStream;
const MCAsmInfo &MAI;
const MCInstrInfo &MII;
@ -61,19 +61,18 @@ public:
virtual ~MCInstPrinter();
/// setCommentStream - Specify a stream to emit comments to.
/// \brief Specify a stream to emit comments to.
void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }
/// printInst - Print the specified MCInst to the specified raw_ostream.
///
/// \brief Print the specified MCInst to the specified raw_ostream.
virtual void printInst(const MCInst *MI, raw_ostream &OS,
StringRef Annot, const MCSubtargetInfo &STI) = 0;
/// getOpcodeName - Return the name of the specified opcode enum (e.g.
/// "MOV32ri") or empty if we can't resolve it.
/// \brief Return the name of the specified opcode enum (e.g. "MOV32ri") or
/// empty if we can't resolve it.
StringRef getOpcodeName(unsigned Opcode) const;
/// printRegName - Print the assembler register name.
/// \brief Print the assembler register name.
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
bool getUseMarkup() const { return UseMarkup; }

4
llvm/include/llvm/MC/MCInstrAnalysis.h
View File

@ -59,8 +59,8 @@ public:
return Info->get(Inst.getOpcode()).isTerminator();
}
/// evaluateBranch - Given a branch instruction try to get the address the
/// branch targets. Return true on success, and the address in Target.
/// \brief Given a branch instruction try to get the address the branch
/// targets. Return true on success, and the address in Target.
virtual bool
evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const;

447
llvm/include/llvm/MC/MCInstrDesc.h
View File

@ -27,130 +27,125 @@ namespace llvm {
//===----------------------------------------------------------------------===//
namespace MCOI {
// Operand constraints
enum OperandConstraint {
TIED_TO = 0, // Must be allocated the same register as.
EARLY_CLOBBER // Operand is an early clobber register operand
};
// Operand constraints
enum OperandConstraint {
TIED_TO = 0, // Must be allocated the same register as.
EARLY_CLOBBER // Operand is an early clobber register operand
};
/// OperandFlags - These are flags set on operands, but should be considered
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags {
LookupPtrRegClass = 0,
Predicate,
OptionalDef
};
/// \brief These are flags set on operands, but should be considered
/// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are.
enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
/// Operand Type - Operands are tagged with one of the values of this enum.
enum OperandType {
OPERAND_UNKNOWN = 0,
OPERAND_IMMEDIATE = 1,
OPERAND_REGISTER = 2,
OPERAND_MEMORY = 3,
OPERAND_PCREL = 4,
OPERAND_FIRST_TARGET = 5
};
/// \brief Operands are tagged with one of the values of this enum.
enum OperandType {
OPERAND_UNKNOWN = 0,
OPERAND_IMMEDIATE = 1,
OPERAND_REGISTER = 2,
OPERAND_MEMORY = 3,
OPERAND_PCREL = 4,
OPERAND_FIRST_TARGET = 5
};
}
/// MCOperandInfo - This holds information about one operand of a machine
/// instruction, indicating the register class for register operands, etc.
///
/// \brief This holds information about one operand of a machine instruction,
/// indicating the register class for register operands, etc.
class MCOperandInfo {
public:
/// RegClass - This specifies the register class enumeration of the operand
/// \brief This specifies the register class enumeration of the operand
/// if the operand is a register. If isLookupPtrRegClass is set, then this is
/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
/// get a dynamic register class.
int16_t RegClass;
/// Flags - These are flags from the MCOI::OperandFlags enum.
/// \brief These are flags from the MCOI::OperandFlags enum.
uint8_t Flags;
/// OperandType - Information about the type of the operand.
/// \brief Information about the type of the operand.
uint8_t OperandType;
/// Lower 16 bits are used to specify which constraints are set. The higher 16
/// bits are used to specify the value of constraints (4 bits each).
/// \brief The lower 16 bits are used to specify which constraints are set.
/// The higher 16 bits are used to specify the value of constraints (4 bits
/// each).
uint32_t Constraints;
/// Currently no other information.
/// isLookupPtrRegClass - Set if this operand is a pointer value and it
/// requires a callback to look up its register class.
bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);}
/// \brief Set if this operand is a pointer value and it requires a callback
/// to look up its register class.
bool isLookupPtrRegClass() const {
return Flags & (1 << MCOI::LookupPtrRegClass);
}
/// isPredicate - Set if this is one of the operands that made up of
/// the predicate operand that controls an isPredicable() instruction.
/// \brief Set if this is one of the operands that made up of the predicate
/// operand that controls an isPredicable() instruction.
bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
/// isOptionalDef - Set if this operand is a optional def.
///
/// \brief Set if this operand is a optional def.
bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
};
//===----------------------------------------------------------------------===//
// Machine Instruction Flags and Description
//===----------------------------------------------------------------------===//
/// MCInstrDesc flags - These should be considered private to the
/// implementation of the MCInstrDesc class. Clients should use the predicate
/// methods on MCInstrDesc, not use these directly. These all correspond to
/// bitfields in the MCInstrDesc::Flags field.
namespace MCID {
enum {
Variadic = 0,
HasOptionalDef,
Pseudo,
Return,
Call,
Barrier,
Terminator,
Branch,
IndirectBranch,
Compare,
MoveImm,
Bitcast,
Select,
DelaySlot,
FoldableAsLoad,
MayLoad,
MayStore,
Predicable,
NotDuplicable,
UnmodeledSideEffects,
Commutable,
ConvertibleTo3Addr,
UsesCustomInserter,
HasPostISelHook,
Rematerializable,
CheapAsAMove,
ExtraSrcRegAllocReq,
ExtraDefRegAllocReq,
RegSequence,
ExtractSubreg,
InsertSubreg
};
/// \brief These should be considered private to the implementation of the
/// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
/// not use these directly. These all correspond to bitfields in the
/// MCInstrDesc::Flags field.
enum Flag {
Variadic = 0,
HasOptionalDef,
Pseudo,
Return,
Call,
Barrier,
Terminator,
Branch,
IndirectBranch,
Compare,
MoveImm,
Bitcast,
Select,
DelaySlot,
FoldableAsLoad,
MayLoad,
MayStore,
Predicable,
NotDuplicable,
UnmodeledSideEffects,
Commutable,
ConvertibleTo3Addr,
UsesCustomInserter,
HasPostISelHook,
Rematerializable,
CheapAsAMove,
ExtraSrcRegAllocReq,
ExtraDefRegAllocReq,
RegSequence,
ExtractSubreg,
InsertSubreg
};
}
/// MCInstrDesc - Describe properties that are true of each instruction in the
/// target description file. This captures information about side effects,
/// register use and many other things. There is one instance of this struct
/// for each target instruction class, and the MachineInstr class points to
/// this struct directly to describe itself.
/// \brief Describe properties that are true of each instruction in the target
/// description file. This captures information about side effects, register
/// use and many other things. There is one instance of this struct for each
/// target instruction class, and the MachineInstr class points to this struct
/// directly to describe itself.
class MCInstrDesc {
public:
unsigned short Opcode; // The opcode number
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned short NumDefs; // Num of args that are definitions
unsigned short SchedClass; // enum identifying instr sched class
unsigned short Size; // Number of bytes in encoding.
unsigned Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
const uint16_t *ImplicitUses; // Registers implicitly read by this instr
const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
unsigned short Opcode; // The opcode number
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned short NumDefs; // Num of args that are definitions
unsigned short SchedClass; // enum identifying instr sched class
unsigned short Size; // Number of bytes in encoding.
unsigned Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
const uint16_t *ImplicitUses; // Registers implicitly read by this instr
const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
uint64_t
DeprecatedFeatureMask; // Feature bits that this is deprecated on, if any
// A complex method to determine is a certain is deprecated or not, and return
// the reason for deprecation.
bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
@ -182,26 +177,20 @@ public:
}
/// \brief Return the opcode number for this descriptor.
unsigned getOpcode() const {
return Opcode;
}
unsigned getOpcode() const { return Opcode; }
/// \brief Return the number of declared MachineOperands for this
/// MachineInstruction. Note that variadic (isVariadic() returns true)
/// instructions may have additional operands at the end of the list, and note
/// that the machine instruction may include implicit register def/uses as
/// well.
unsigned getNumOperands() const {
return NumOperands;
}
unsigned getNumOperands() const { return NumOperands; }
/// \brief Return the number of MachineOperands that are register
/// definitions. Register definitions always occur at the start of the
/// machine operand list. This is the number of "outs" in the .td file,
/// and does not include implicit defs.
unsigned getNumDefs() const {
return NumDefs;
}
unsigned getNumDefs() const { return NumDefs; }
/// \brief Return flags of this instruction.
unsigned getFlags() const { return Flags; }
@ -210,39 +199,26 @@ public:
/// operands. In this case, the variable operands will be after the normal
/// operands but before the implicit definitions and uses (if any are
/// present).
bool isVariadic() const {
return Flags & (1 << MCID::Variadic);
}
bool isVariadic() const { return Flags & (1 << MCID::Variadic); }
/// \brief Set if this instruction has an optional definition, e.g.
/// ARM instructions which can set condition code if 's' bit is set.
bool hasOptionalDef() const {
return Flags & (1 << MCID::HasOptionalDef);
}
bool hasOptionalDef() const { return Flags & (1 << MCID::HasOptionalDef); }
/// \brief Return true if this is a pseudo instruction that doesn't
/// correspond to a real machine instruction.
///
bool isPseudo() const {
return Flags & (1 << MCID::Pseudo);
}
bool isPseudo() const { return Flags & (1 << MCID::Pseudo); }
/// \brief Return true if the instruction is a return.
bool isReturn() const {
return Flags & (1 << MCID::Return);
}
bool isReturn() const { return Flags & (1 << MCID::Return); }
/// \brief Return true if the instruction is a call.
bool isCall() const {
return Flags & (1 << MCID::Call);
}
bool isCall() const { return Flags & (1 << MCID::Call); }
/// \brief Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions.
bool isBarrier() const {
return Flags & (1 << MCID::Barrier);
}
bool isBarrier() const { return Flags & (1 << MCID::Barrier); }
/// \brief Returns true if this instruction part of the terminator for
/// a basic block. Typically this is things like return and branch
@ -250,23 +226,17 @@ public:
///
/// Various passes use this to insert code into the bottom of a basic block,
/// but before control flow occurs.
bool isTerminator() const {
return Flags & (1 << MCID::Terminator);
}
bool isTerminator() const { return Flags & (1 << MCID::Terminator); }
/// \brief Returns true if this is a conditional, unconditional, or
/// indirect branch. Predicates below can be used to discriminate between
/// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
/// get more information.
bool isBranch() const {
return Flags & (1 << MCID::Branch);
}
bool isBranch() const { return Flags & (1 << MCID::Branch); }
/// \brief Return true if this is an indirect branch, such as a
/// branch through a register.
bool isIndirectBranch() const {
return Flags & (1 << MCID::IndirectBranch);
}
bool isIndirectBranch() const { return Flags & (1 << MCID::IndirectBranch); }
/// \brief Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
@ -311,55 +281,38 @@ public:
/// that controls execution. It may be set to 'always', or may be set to other
/// values. There are various methods in TargetInstrInfo that can be used to
/// control and modify the predicate in this instruction.
bool isPredicable() const {
return Flags & (1 << MCID::Predicable);
}
bool isPredicable() const { return Flags & (1 << MCID::Predicable); }
/// \brief Return true if this instruction is a comparison.
bool isCompare() const {
return Flags & (1 << MCID::Compare);
}
bool isCompare() const { return Flags & (1 << MCID::Compare); }
/// \brief Return true if this instruction is a move immediate
/// (including conditional moves) instruction.
bool isMoveImmediate() const {
return Flags & (1 << MCID::MoveImm);
}
bool isMoveImmediate() const { return Flags & (1 << MCID::MoveImm); }
/// \brief Return true if this instruction is a bitcast instruction.
bool isBitcast() const {
return Flags & (1 << MCID::Bitcast);
}
bool isBitcast() const { return Flags & (1 << MCID::Bitcast); }
/// \brief Return true if this is a select instruction.
bool isSelect() const {
return Flags & (1 << MCID::Select);
}
bool isSelect() const { return Flags & (1 << MCID::Select); }
/// \brief Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable() const {
return Flags & (1 << MCID::NotDuplicable);
}
bool isNotDuplicable() const { return Flags & (1 << MCID::NotDuplicable); }
/// hasDelaySlot - Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot() const {
return Flags & (1 << MCID::DelaySlot);
}
/// \brief Returns true if the specified instruction has a delay slot which
/// must be filled by the code generator.
bool hasDelaySlot() const { return Flags & (1 << MCID::DelaySlot); }
/// canFoldAsLoad - Return true for instructions that can be folded as
/// memory operands in other instructions. The most common use for this
/// is instructions that are simple loads from memory that don't modify
/// the loaded value in any way, but it can also be used for instructions
/// that can be expressed as constant-pool loads, such as V_SETALLONES
/// on x86, to allow them to be folded when it is beneficial.
/// This should only be set on instructions that return a value in their
/// only virtual register definition.
bool canFoldAsLoad() const {
return Flags & (1 << MCID::FoldableAsLoad);
}
/// \brief Return true for instructions that can be folded as memory operands
/// in other instructions. The most common use for this is instructions that
/// are simple loads from memory that don't modify the loaded value in any
/// way, but it can also be used for instructions that can be expressed as
/// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
/// folded when it is beneficial. This should only be set on instructions
/// that return a value in their only virtual register definition.
bool canFoldAsLoad() const { return Flags & (1 << MCID::FoldableAsLoad); }
/// \brief Return true if this instruction behaves
/// the same way as the generic REG_SEQUENCE instructions.
@ -398,9 +351,7 @@ public:
/// Note that for the optimizers to be able to take advantage of
/// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
/// override accordingly.
bool isInsertSubregLike() const {
return Flags & (1 << MCID::InsertSubreg);
}
bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); }
//===--------------------------------------------------------------------===//
// Side Effect Analysis
@ -409,20 +360,15 @@ public:
/// \brief Return true if this instruction could possibly read memory.
/// Instructions with this flag set are not necessarily simple load
/// instructions, they may load a value and modify it, for example.
bool mayLoad() const {
return Flags & (1 << MCID::MayLoad);
}
bool mayLoad() const { return Flags & (1 << MCID::MayLoad); }
/// \brief Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example.
bool mayStore() const {
return Flags & (1 << MCID::MayStore);
}
bool mayStore() const { return Flags & (1 << MCID::MayStore); }
/// hasUnmodeledSideEffects - Return true if this instruction has side
/// \brief Return true if this instruction has side
/// effects that are not modeled by other flags. This does not return true
/// for instructions whose effects are captured by:
///
@ -434,7 +380,6 @@ public:
/// Examples of side effects would be modifying 'invisible' machine state like
/// a control register, flushing a cache, modifying a register invisible to
/// LLVM, etc.
///
bool hasUnmodeledSideEffects() const {
return Flags & (1 << MCID::UnmodeledSideEffects);
}
@ -443,9 +388,9 @@ public:
// Flags that indicate whether an instruction can be modified by a method.
//===--------------------------------------------------------------------===//
/// isCommutable - Return true if this may be a 2- or 3-address
/// instruction (of the form "X = op Y, Z, ..."), which produces the same
/// result if Y and Z are exchanged. If this flag is set, then the
/// \brief Return true if this may be a 2- or 3-address instruction (of the
/// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
/// exchanged. If this flag is set, then the
/// TargetInstrInfo::commuteInstruction method may be used to hack on the
/// instruction.
///
@ -453,18 +398,16 @@ public:
/// sometimes. In these cases, the call to commuteInstruction will fail.
/// Also note that some instructions require non-trivial modification to
/// commute them.
bool isCommutable() const {
return Flags & (1 << MCID::Commutable);
}
bool isCommutable() const { return Flags & (1 << MCID::Commutable); }
/// isConvertibleTo3Addr - Return true if this is a 2-address instruction
/// which can be changed into a 3-address instruction if needed. Doing this
/// transformation can be profitable in the register allocator, because it
/// means that the instruction can use a 2-address form if possible, but
/// degrade into a less efficient form if the source and dest register cannot
/// be assigned to the same register. For example, this allows the x86
/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
/// is the same speed as the shift but has bigger code size.
/// \brief Return true if this is a 2-address instruction which can be changed
/// into a 3-address instruction if needed. Doing this transformation can be
/// profitable in the register allocator, because it means that the
/// instruction can use a 2-address form if possible, but degrade into a less
/// efficient form if the source and dest register cannot be assigned to the
/// same register. For example, this allows the x86 backend to turn a "shl
/// reg, 3" instruction into an LEA instruction, which is the same speed as
/// the shift but has bigger code size.
///
/// If this returns true, then the target must implement the
/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
@ -475,11 +418,11 @@ public:
return Flags & (1 << MCID::ConvertibleTo3Addr);
}
/// usesCustomInsertionHook - Return true if this instruction requires
/// custom insertion support when the DAG scheduler is inserting it into a
/// machine basic block. If this is true for the instruction, it basically
/// means that it is a pseudo instruction used at SelectionDAG time that is
/// expanded out into magic code by the target when MachineInstrs are formed.
/// \brief Return true if this instruction requires custom insertion support
/// when the DAG scheduler is inserting it into a machine basic block. If
/// this is true for the instruction, it basically means that it is a pseudo
/// instruction used at SelectionDAG time that is expanded out into magic code
/// by the target when MachineInstrs are formed.
///
/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
/// is used to insert this into the MachineBasicBlock.
@ -487,17 +430,14 @@ public:
return Flags & (1 << MCID::UsesCustomInserter);
}
/// hasPostISelHook - Return true if this instruction requires *adjustment*
/// after instruction selection by calling a target hook. For example, this
/// can be used to fill in ARM 's' optional operand depending on whether
/// the conditional flag register is used.
bool hasPostISelHook() const {
return Flags & (1 << MCID::HasPostISelHook);
}
/// \brief Return true if this instruction requires *adjustment* after
/// instruction selection by calling a target hook. For example, this can be
/// used to fill in ARM 's' optional operand depending on whether the
/// conditional flag register is used.
bool hasPostISelHook() const { return Flags & (1 << MCID::HasPostISelHook); }
/// isRematerializable - Returns true if this instruction is a candidate for
/// remat. This flag is only used in TargetInstrInfo method
/// isTriviallyRematerializable.
/// \brief Returns true if this instruction is a candidate for remat. This
/// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
///
/// If this flag is set, the isReallyTriviallyReMaterializable()
/// or isReallyTriviallyReMaterializableGeneric methods are called to verify
@ -506,80 +446,76 @@ public:
return Flags & (1 << MCID::Rematerializable);
}
/// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
/// less) than a move instruction. This is useful during certain types of
/// optimizations (e.g., remat during two-address conversion or machine licm)
/// where we would like to remat or hoist the instruction, but not if it costs
/// more than moving the instruction into the appropriate register. Note, we
/// are not marking copies from and to the same register class with this flag.
/// \brief Returns true if this instruction has the same cost (or less) than a
/// move instruction. This is useful during certain types of optimizations
/// (e.g., remat during two-address conversion or machine licm) where we would
/// like to remat or hoist the instruction, but not if it costs more than
/// moving the instruction into the appropriate register. Note, we are not
/// marking copies from and to the same register class with this flag.
///
/// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
/// for different subtargets.
bool isAsCheapAsAMove() const {
return Flags & (1 << MCID::CheapAsAMove);
}
bool isAsCheapAsAMove() const { return Flags & (1 << MCID::CheapAsAMove); }
/// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
/// have special register allocation requirements that are not captured by the
/// operand register classes. e.g. ARM::STRD's two source registers must be an
/// even / odd pair, ARM::STM registers have to be in ascending order.
/// Post-register allocation passes should not attempt to change allocations
/// for sources of instructions with this flag.
/// \brief Returns true if this instruction source operands have special
/// register allocation requirements that are not captured by the operand
/// register classes. e.g. ARM::STRD's two source registers must be an even /
/// odd pair, ARM::STM registers have to be in ascending order. Post-register
/// allocation passes should not attempt to change allocations for sources of
/// instructions with this flag.
bool hasExtraSrcRegAllocReq() const {
return Flags & (1 << MCID::ExtraSrcRegAllocReq);
}
/// hasExtraDefRegAllocReq - Returns true if this instruction def operands
/// have special register allocation requirements that are not captured by the
/// operand register classes. e.g. ARM::LDRD's two def registers must be an
/// even / odd pair, ARM::LDM registers have to be in ascending order.
/// Post-register allocation passes should not attempt to change allocations
/// for definitions of instructions with this flag.
/// \brief Returns true if this instruction def operands have special register
/// allocation requirements that are not captured by the operand register
/// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
/// ARM::LDM registers have to be in ascending order. Post-register
/// allocation passes should not attempt to change allocations for definitions
/// of instructions with this flag.
bool hasExtraDefRegAllocReq() const {
return Flags & (1 << MCID::ExtraDefRegAllocReq);
}
/// getImplicitUses - Return a list of registers that are potentially
/// read by any instance of this machine instruction. For example, on X86,
/// the "adc" instruction adds two register operands and adds the carry bit in
/// from the flags register. In this case, the instruction is marked as
/// implicitly reading the flags. Likewise, the variable shift instruction on
/// X86 is marked as implicitly reading the 'CL' register, which it always
/// does.
/// \brief Return a list of registers that are potentially read by any
/// instance of this machine instruction. For example, on X86, the "adc"
/// instruction adds two register operands and adds the carry bit in from the
/// flags register. In this case, the instruction is marked as implicitly
/// reading the flags. Likewise, the variable shift instruction on X86 is
/// marked as implicitly reading the 'CL' register, which it always does.
///
/// This method returns null if the instruction has no implicit uses.
const uint16_t *getImplicitUses() const {
return ImplicitUses;
}
const uint16_t *getImplicitUses() const { return ImplicitUses; }
/// \brief Return the number of implicit uses this instruction has.
unsigned getNumImplicitUses() const {
if (!ImplicitUses) return 0;
if (!ImplicitUses)
return 0;
unsigned i = 0;
for (; ImplicitUses[i]; ++i) /*empty*/;
for (; ImplicitUses[i]; ++i) /*empty*/
;
return i;
}
/// getImplicitDefs - Return a list of registers that are potentially
/// written by any instance of this machine instruction. For example, on X86,
/// many instructions implicitly set the flags register. In this case, they
/// are marked as setting the FLAGS. Likewise, many instructions always
/// deposit their result in a physical register. For example, the X86 divide
/// \brief Return a list of registers that are potentially written by any
/// instance of this machine instruction. For example, on X86, many
/// instructions implicitly set the flags register. In this case, they are
/// marked as setting the FLAGS. Likewise, many instructions always deposit
/// their result in a physical register. For example, the X86 divide
/// instruction always deposits the quotient and remainder in the EAX/EDX
/// registers. For that instruction, this will return a list containing the
/// EAX/EDX/EFLAGS registers.
///
/// This method returns null if the instruction has no implicit defs.
const uint16_t *getImplicitDefs() const {
return ImplicitDefs;
}
const uint16_t *getImplicitDefs() const { return ImplicitDefs; }
/// \brief Return the number of implicit defs this instruct has.
unsigned getNumImplicitDefs() const {
if (!ImplicitDefs) return 0;
if (!ImplicitDefs)
return 0;
unsigned i = 0;
for (; ImplicitDefs[i]; ++i) /*empty*/;
for (; ImplicitDefs[i]; ++i) /*empty*/
;
return i;
}
@ -588,7 +524,8 @@ public:
bool hasImplicitUseOfPhysReg(unsigned Reg) const {
if (const uint16_t *ImpUses = ImplicitUses)
for (; *ImpUses; ++ImpUses)
if (*ImpUses == Reg) return true;
if (*ImpUses == Reg)
return true;
return false;
}
@ -599,7 +536,7 @@ public:
if (const uint16_t *ImpDefs = ImplicitDefs)
for (; *ImpDefs; ++ImpDefs)
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
return true;
return true;
return false;
}
@ -618,15 +555,11 @@ public:
/// scheduling class is an index into the InstrItineraryData table. This
/// returns zero if there is no known scheduling information for the
/// instruction.
unsigned getSchedClass() const {
return SchedClass;
}
unsigned getSchedClass() const { return SchedClass; }
/// \brief Return the number of bytes in the encoding of this instruction,
/// or zero if the encoding size cannot be known from the opcode.
unsigned getSize() const {
return Size;
}
unsigned getSize() const { return Size; }
/// \brief Find the index of the first operand in the
/// operand list that is used to represent the predicate. It returns -1 if

13
llvm/include/llvm/MC/MCInstrInfo.h
View File

@ -20,9 +20,7 @@
namespace llvm {
//---------------------------------------------------------------------------
///
/// MCInstrInfo - Interface to description of machine instruction set
///
/// \brief Interface to description of machine instruction set.
class MCInstrInfo {
const MCInstrDesc *Desc; // Raw array to allow static init'n
const unsigned *InstrNameIndices; // Array for name indices in InstrNameData
@ -30,8 +28,8 @@ class MCInstrInfo {
unsigned NumOpcodes; // Number of entries in the desc array
public:
/// InitMCInstrInfo - Initialize MCInstrInfo, called by TableGen
/// auto-generated routines. *DO NOT USE*.
/// \brief Initialize MCInstrInfo, called by TableGen auto-generated routines.
/// *DO NOT USE*.
void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND,
unsigned NO) {
Desc = D;
@ -42,15 +40,14 @@ public:
unsigned getNumOpcodes() const { return NumOpcodes; }
/// get - Return the machine instruction descriptor that corresponds to the
/// \brief Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const MCInstrDesc &get(unsigned Opcode) const {
assert(Opcode < NumOpcodes && "Invalid opcode!");
return Desc[Opcode];
}
/// getName - Returns the name for the instructions with the given opcode.
/// \brief Returns the name for the instructions with the given opcode.
const char *getName(unsigned Opcode) const {
assert(Opcode < NumOpcodes && "Invalid opcode!");
return &InstrNameData[InstrNameIndices[Opcode]];

45
llvm/include/llvm/MC/MCInstrItineraries.h
View File

@ -67,12 +67,12 @@ struct InstrStage {
int NextCycles_; ///< Number of machine cycles to next stage
ReservationKinds Kind_; ///< Kind of the FU reservation
/// Returns the number of cycles the stage is occupied.
/// \brief Returns the number of cycles the stage is occupied.
unsigned getCycles() const {
return Cycles_;
}
/// Returns the choice of FUs.
/// \brief Returns the choice of FUs.
unsigned getUnits() const {
return Units_;
}
@ -81,8 +81,8 @@ struct InstrStage {
return Kind_;
}
/// Returns the number of cycles from the start of
/// this stage to the start of the next stage in the itinerary
/// \brief Returns the number of cycles from the start of this stage to the
/// start of the next stage in the itinerary
unsigned getNextCycles() const {
return (NextCycles_ >= 0) ? (unsigned)NextCycles_ : Cycles_;
}
@ -115,7 +115,6 @@ public:
const InstrItinerary *Itineraries; ///< Array of itineraries selected
/// Ctors.
///
InstrItineraryData() : SchedModel(MCSchedModel::GetDefaultSchedModel()),
Stages(nullptr), OperandCycles(nullptr),
Forwardings(nullptr), Itineraries(nullptr) {}
@ -125,30 +124,30 @@ public:
: SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
Itineraries(SchedModel.InstrItineraries) {}
/// Returns true if there are no itineraries.
/// \brief Returns true if there are no itineraries.
bool isEmpty() const { return Itineraries == nullptr; }
/// Returns true if the index is for the end marker itinerary.
/// \brief Returns true if the index is for the end marker itinerary.
bool isEndMarker(unsigned ItinClassIndx) const {
return ((Itineraries[ItinClassIndx].FirstStage == ~0U) &&
(Itineraries[ItinClassIndx].LastStage == ~0U));
}
/// Return the first stage of the itinerary.
/// \brief Return the first stage of the itinerary.
const InstrStage *beginStage(unsigned ItinClassIndx) const {
unsigned StageIdx = Itineraries[ItinClassIndx].FirstStage;
return Stages + StageIdx;
}
/// Return the last+1 stage of the itinerary.
/// \brief Return the last+1 stage of the itinerary.
const InstrStage *endStage(unsigned ItinClassIndx) const {
unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;
return Stages + StageIdx;
}
/// Return the total stage latency of the given class.
/// The latency is the maximum completion time for any stage in the itinerary.
/// If no stages exist, it defaults to one cycle.
/// \brief Return the total stage latency of the given class. The latency is
/// the maximum completion time for any stage in the itinerary. If no stages
/// exist, it defaults to one cycle.
unsigned getStageLatency(unsigned ItinClassIndx) const {
// If the target doesn't provide itinerary information, use a simple
// non-zero default value for all instructions.
@ -165,8 +164,8 @@ public:
return Latency;
}
/// Return the cycle for the given class and operand.
/// Return -1 if no cycle is specified for the operand.
/// \brief Return the cycle for the given class and operand. Return -1 if no
/// cycle is specified for the operand.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const {
if (isEmpty())
return -1;
@ -179,11 +178,11 @@ public:
return (int)OperandCycles[FirstIdx + OperandIdx];
}
/// Return true if there is a pipeline forwarding
/// between instructions of itinerary classes DefClass and UseClasses so that
/// value produced by an instruction of itinerary class DefClass, operand
/// index DefIdx can be bypassed when it's read by an instruction of
/// itinerary class UseClass, operand index UseIdx.
/// \brief Return true if there is a pipeline forwarding between instructions
/// of itinerary classes DefClass and UseClasses so that value produced by an
/// instruction of itinerary class DefClass, operand index DefIdx can be
/// bypassed when it's read by an instruction of itinerary class UseClass,
/// operand index UseIdx.
bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
unsigned UseClass, unsigned UseIdx) const {
unsigned FirstDefIdx = Itineraries[DefClass].FirstOperandCycle;
@ -202,9 +201,9 @@ public:
Forwardings[FirstUseIdx + UseIdx];
}
/// Compute and return the use operand latency of a given
/// itinerary class and operand index if the value is produced by an
/// instruction of the specified itinerary class and def operand index.
/// \brief Compute and return the use operand latency of a given itinerary
/// class and operand index if the value is produced by an instruction of the
/// specified itinerary class and def operand index.
int getOperandLatency(unsigned DefClass, unsigned DefIdx,
unsigned UseClass, unsigned UseIdx) const {
if (isEmpty())
@ -226,7 +225,7 @@ public:
return UseCycle;
}
/// Return the number of micro-ops that the given class decodes to.
/// \brief Return the number of micro-ops that the given class decodes to.
/// Return -1 for classes that require dynamic lookup via TargetInstrInfo.
int getNumMicroOps(unsigned ItinClassIndx) const {
if (isEmpty())

13
llvm/include/llvm/MC/MCLabel.h
View File

@ -20,11 +20,11 @@ namespace llvm {
class MCContext;
class raw_ostream;
/// MCLabel - Instances of this class represent a label name in the MC file,
/// \brief Instances of this class represent a label name in the MC file,
/// and MCLabel are created and uniqued by the MCContext class. MCLabel
/// should only be constructed for valid instances in the object file.
class MCLabel {
// Instance - the instance number of this Directional Local Label
// \brief The instance number of this Directional Local Label.
unsigned Instance;
private: // MCContext creates and uniques these.
@ -35,17 +35,16 @@ namespace llvm {
MCLabel(const MCLabel&) = delete;
void operator=(const MCLabel&) = delete;
public:
/// getInstance - Get the current instance of this Directional Local Label.
/// \brief Get the current instance of this Directional Local Label.
unsigned getInstance() const { return Instance; }
/// incInstance - Increment the current instance of this Directional Local
/// Label.
/// \brief Increment the current instance of this Directional Local Label.
unsigned incInstance() { return ++Instance; }
/// print - Print the value to the stream \p OS.
/// \brief Print the value to the stream \p OS.
void print(raw_ostream &OS) const;
/// dump - Print the value to stderr.
/// \brief Print the value to stderr.
void dump() const;
};

12
llvm/include/llvm/MC/MCLinkerOptimizationHint.h
View File

@ -103,8 +103,8 @@ class MCLOHDirective {
/// Arguments of this directive. Order matters.
SmallVector<MCSymbol *, 3> Args;
/// Emit this directive in @p OutStream using the information available
/// in the given @p ObjWriter and @p Layout to get the address of the
/// Emit this directive in \p OutStream using the information available
/// in the given \p ObjWriter and \p Layout to get the address of the
/// arguments within the object file.
void Emit_impl(raw_ostream &OutStream, const MachObjectWriter &ObjWriter,
const MCAsmLayout &Layout) const;
@ -128,8 +128,8 @@ public:
Emit_impl(OutStream, ObjWriter, Layout);
}
/// Get the size in bytes of this directive if emitted in @p ObjWriter with
/// the given @p Layout.
/// Get the size in bytes of this directive if emitted in \p ObjWriter with
/// the given \p Layout.
uint64_t getEmitSize(const MachObjectWriter &ObjWriter,
const MCAsmLayout &Layout) const {
class raw_counting_ostream : public raw_ostream {
@ -167,8 +167,8 @@ public:
return Directives;
}
/// Add the directive of the given kind @p Kind with the given arguments
/// @p Args to the container.
/// Add the directive of the given kind \p Kind with the given arguments
/// \p Args to the container.
void addDirective(MCLOHType Kind, const MCLOHDirective::LOHArgs &Args) {
Directives.push_back(MCLOHDirective(Kind, Args));
}

16
llvm/include/llvm/MC/MCMachObjectWriter.h
View File

@ -45,14 +45,14 @@ protected:
public:
virtual ~MCMachObjectTargetWriter();
/// @name Lifetime Management
/// \name Lifetime Management
/// @{
virtual void reset() {};
/// @}
/// @name Accessors
/// \name Accessors
/// @{
bool is64Bit() const { return Is64Bit; }
@ -65,7 +65,7 @@ public:
/// @}
/// @name API
/// \name API
/// @{
virtual void RecordRelocation(MachObjectWriter *Writer, MCAssembler &Asm,
@ -92,7 +92,7 @@ class MachObjectWriter : public MCObjectWriter {
/// The target specific Mach-O writer instance.
std::unique_ptr<MCMachObjectTargetWriter> TargetObjectWriter;
/// @name Relocation Data
/// \name Relocation Data
/// @{
struct RelAndSymbol {
@ -106,7 +106,7 @@ class MachObjectWriter : public MCObjectWriter {
llvm::DenseMap<const MCSectionData*, unsigned> IndirectSymBase;
/// @}
/// @name Symbol Table Data
/// \name Symbol Table Data
/// @{
StringTableBuilder StringTable;
@ -125,14 +125,14 @@ public:
const MCSymbol &findAliasedSymbol(const MCSymbol &Sym) const;
/// @name Lifetime management Methods
/// \name Lifetime management Methods
/// @{
void reset() override;
/// @}
/// @name Utility Methods
/// \name Utility Methods
/// @{
bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind);
@ -157,7 +157,7 @@ public:
/// @}
/// @name Target Writer Proxy Accessors
/// \name Target Writer Proxy Accessors
/// @{
bool is64Bit() const { return TargetObjectWriter->is64Bit(); }

2
llvm/include/llvm/MC/MCObjectStreamer.h
View File

@ -93,7 +93,7 @@ public:
MCAssembler &getAssembler() { return *Assembler; }
/// @name MCStreamer Interface
/// \name MCStreamer Interface
/// @{
void EmitLabel(MCSymbol *Symbol) override;

4
llvm/include/llvm/MC/MCObjectWriter.h
View File

@ -60,7 +60,7 @@ public:
raw_ostream &getStream() { return OS; }
/// @name High-Level API
/// \name High-Level API
/// @{
/// \brief Perform any late binding of symbols (for example, to assign symbol
@ -112,7 +112,7 @@ public:
const MCAsmLayout &Layout) = 0;
/// @}
/// @name Binary Output
/// \name Binary Output
/// @{
void Write8(uint8_t Value) {

68
llvm/include/llvm/MC/MCParser/MCAsmParser.h
View File

@ -45,7 +45,7 @@ public:
}
};
/// Generic Sema callback for assembly parser.
/// \brief Generic Sema callback for assembly parser.
class MCAsmParserSemaCallback {
public:
virtual ~MCAsmParserSemaCallback();
@ -59,8 +59,8 @@ public:
unsigned &Offset) = 0;
};
/// Generic assembler parser interface, for use by target specific assembly
/// parsers.
/// \brief Generic assembler parser interface, for use by target specific
/// assembly parsers.
class MCAsmParser {
public:
typedef bool (*DirectiveHandler)(MCAsmParserExtension*, StringRef, SMLoc);
@ -95,7 +95,7 @@ public:
virtual MCContext &getContext() = 0;
/// Return the output streamer for the assembler.
/// \brief Return the output streamer for the assembler.
virtual MCStreamer &getStreamer() = 0;
MCTargetAsmParser &getTargetParser() const { return *TargetParser; }
@ -107,13 +107,13 @@ public:
bool getShowParsedOperands() const { return ShowParsedOperands; }
void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; }
/// Run the parser on the input source buffer.
/// \brief Run the parser on the input source buffer.
virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0;
virtual void setParsingInlineAsm(bool V) = 0;
virtual bool isParsingInlineAsm() = 0;
/// Parse ms-style inline assembly.
/// \brief Parse MS-style inline assembly.
virtual bool parseMSInlineAsm(
void *AsmLoc, std::string &AsmString, unsigned &NumOutputs,
unsigned &NumInputs, SmallVectorImpl<std::pair<void *, bool>> &OpDecls,
@ -121,35 +121,35 @@ public:
SmallVectorImpl<std::string> &Clobbers, const MCInstrInfo *MII,
const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0;
/// Emit a note at the location \p L, with the message \p Msg.
/// \brief Emit a note at the location \p L, with the message \p Msg.
virtual void Note(SMLoc L, const Twine &Msg,
ArrayRef<SMRange> Ranges = None) = 0;
/// Emit a warning at the location \p L, with the message \p Msg.
/// \brief Emit a warning at the location \p L, with the message \p Msg.
///
/// \return The return value is true, if warnings are fatal.
virtual bool Warning(SMLoc L, const Twine &Msg,
ArrayRef<SMRange> Ranges = None) = 0;
/// Emit an error at the location \p L, with the message \p Msg.
/// \brief Emit an error at the location \p L, with the message \p Msg.
///
/// \return The return value is always true, as an idiomatic convenience to
/// clients.
virtual bool Error(SMLoc L, const Twine &Msg,
ArrayRef<SMRange> Ranges = None) = 0;
/// Get the next AsmToken in the stream, possibly handling file inclusion
/// first.
/// \brief Get the next AsmToken in the stream, possibly handling file
/// inclusion first.
virtual const AsmToken &Lex() = 0;
/// Get the current AsmToken from the stream.
/// \brief Get the current AsmToken from the stream.
const AsmToken &getTok() const;
/// \brief Report an error at the current lexer location.
bool TokError(const Twine &Msg, ArrayRef<SMRange> Ranges = None);
/// Parse an identifier or string (as a quoted identifier) and set \p Res to
/// the identifier contents.
/// \brief Parse an identifier or string (as a quoted identifier) and set \p
/// Res to the identifier contents.
virtual bool parseIdentifier(StringRef &Res) = 0;
/// \brief Parse up to the end of statement and return the contents from the
@ -157,51 +157,51 @@ public:
/// will be either the EndOfStatement or EOF.
virtual StringRef parseStringToEndOfStatement() = 0;
/// Parse the current token as a string which may include escaped characters
/// and return the string contents.
/// \brief Parse the current token as a string which may include escaped
/// characters and return the string contents.
virtual bool parseEscapedString(std::string &Data) = 0;
/// Skip to the end of the current statement, for error recovery.
/// \brief Skip to the end of the current statement, for error recovery.
virtual void eatToEndOfStatement() = 0;
/// Parse an arbitrary expression.
/// \brief Parse an arbitrary expression.
///
/// @param Res - The value of the expression. The result is undefined
/// \param Res - The value of the expression. The result is undefined
/// on error.
/// @result - False on success.
/// \return - False on success.
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc) = 0;
bool parseExpression(const MCExpr *&Res);
/// Parse a primary expression.
/// \brief Parse a primary expression.
///
/// @param Res - The value of the expression. The result is undefined
/// \param Res - The value of the expression. The result is undefined
/// on error.
/// @result - False on success.
/// \return - False on success.
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) = 0;
/// Parse an arbitrary expression, assuming that an initial '(' has already
/// been consumed.
/// \brief Parse an arbitrary expression, assuming that an initial '(' has
/// already been consumed.
///
/// @param Res - The value of the expression. The result is undefined
/// \param Res - The value of the expression. The result is undefined
/// on error.
/// @result - False on success.
/// \return - False on success.
virtual bool parseParenExpression(const MCExpr *&Res, SMLoc &EndLoc) = 0;
/// Parse an expression which must evaluate to an absolute value.
/// \brief Parse an expression which must evaluate to an absolute value.
///
/// @param Res - The value of the absolute expression. The result is undefined
/// \param Res - The value of the absolute expression. The result is undefined
/// on error.
/// @result - False on success.
/// \return - False on success.
virtual bool parseAbsoluteExpression(int64_t &Res) = 0;
/// Ensure that we have a valid section set in the streamer. Otherwise, report
/// an error and switch to .text.
/// \brief Ensure that we have a valid section set in the streamer. Otherwise,
/// report an error and switch to .text.
virtual void checkForValidSection() = 0;
};
/// \brief Create an MCAsmParser instance.
MCAsmParser *createMCAsmParser(SourceMgr &, MCContext &,
MCStreamer &, const MCAsmInfo &);
MCAsmParser *createMCAsmParser(SourceMgr &, MCContext &, MCStreamer &,
const MCAsmInfo &);
} // End llvm namespace

2
llvm/include/llvm/MC/MCParser/MCAsmParserExtension.h
View File

@ -48,7 +48,7 @@ public:
/// parsing routines.
virtual void Initialize(MCAsmParser &Parser);
/// @name MCAsmParser Proxy Interfaces
/// \name MCAsmParser Proxy Interfaces
/// @{
MCContext &getContext() { return getParser().getContext(); }

280
llvm/include/llvm/MC/MCStreamer.h
View File

@ -163,11 +163,12 @@ private:
std::unique_ptr<AssemblerConstantPools> ConstantPools;
};
/// MCStreamer - Streaming machine code generation interface. This interface
/// is intended to provide a programatic interface that is very similar to the
/// level that an assembler .s file provides. It has callbacks to emit bytes,
/// handle directives, etc. The implementation of this interface retains
/// state to know what the current section is etc.
/// \brief Streaming machine code generation interface.
///
/// This interface is intended to provide a programatic interface that is very
/// similar to the level that an assembler .s file provides. It has callbacks
/// to emit bytes, handle directives, etc. The implementation of this interface
/// retains state to know what the current section is etc.
///
/// There are multiple implementations of this interface: one for writing out
/// a .s file, and implementations that write out .o files of various formats.
@ -189,12 +190,12 @@ class MCStreamer {
WinEH::FrameInfo *CurrentWinFrameInfo;
void EnsureValidWinFrameInfo();
// SymbolOrdering - Tracks an index to represent the order
// a symbol was emitted in. Zero means we did not emit that symbol.
/// \brief Tracks an index to represent the order a symbol was emitted in.
/// Zero means we did not emit that symbol.
DenseMap<const MCSymbol *, unsigned> SymbolOrdering;
/// SectionStack - This is stack of current and previous section
/// values saved by PushSection.
/// \brief This is stack of current and previous section values saved by
/// PushSection.
SmallVector<std::pair<MCSectionSubPair, MCSectionSubPair>, 4> SectionStack;
protected:
@ -243,22 +244,24 @@ public:
void generateCompactUnwindEncodings(MCAsmBackend *MAB);
/// @name Assembly File Formatting.
/// \name Assembly File Formatting.
/// @{
/// isVerboseAsm - Return true if this streamer supports verbose assembly
/// and if it is enabled.
/// \brief Return true if this streamer supports verbose assembly and if it is
/// enabled.
virtual bool isVerboseAsm() const { return false; }
/// hasRawTextSupport - Return true if this asm streamer supports emitting
/// unformatted text to the .s file with EmitRawText.
/// \brief Return true if this asm streamer supports emitting unformatted text
/// to the .s file with EmitRawText.
virtual bool hasRawTextSupport() const { return false; }
/// Is the integrated assembler required for this streamer to function
/// \brief Is the integrated assembler required for this streamer to function
/// correctly?
virtual bool isIntegratedAssemblerRequired() const { return false; }
/// AddComment - Add a comment that can be emitted to the generated .s
/// \brief Add a textual command.
///
/// Typically for comments that can be emitted to the generated .s
/// file if applicable as a QoI issue to make the output of the compiler
/// more readable. This only affects the MCAsmStreamer, and only when
/// verbose assembly output is enabled.
@ -267,14 +270,14 @@ public:
/// prefix as appropriate. The added comment should not end with a \n.
virtual void AddComment(const Twine &T) {}
/// GetCommentOS - Return a raw_ostream that comments can be written to.
/// Unlike AddComment, you are required to terminate comments with \n if you
/// use this method.
/// \brief Return a raw_ostream that comments can be written to. Unlike
/// AddComment, you are required to terminate comments with \n if you use this
/// method.
virtual raw_ostream &GetCommentOS();
/// Print T and prefix it with the comment string (normally #) and optionally
/// a tab. This prints the comment immediately, not at the end of the
/// current line. It is basically a safe version of EmitRawText: since it
/// \brief Print T and prefix it with the comment string (normally #) and
/// optionally a tab. This prints the comment immediately, not at the end of
/// the current line. It is basically a safe version of EmitRawText: since it
/// only prints comments, the object streamer ignores it instead of asserting.
virtual void emitRawComment(const Twine &T, bool TabPrefix = true);
@ -283,46 +286,43 @@ public:
/// @}
/// @name Symbol & Section Management
/// \name Symbol & Section Management
/// @{
/// getCurrentSection - Return the current section that the streamer is
/// emitting code to.
/// \brief Return the current section that the streamer is emitting code to.
MCSectionSubPair getCurrentSection() const {
if (!SectionStack.empty())
return SectionStack.back().first;
return MCSectionSubPair();
}
/// getPreviousSection - Return the previous section that the streamer is
/// emitting code to.
/// \brief Return the previous section that the streamer is emitting code to.
MCSectionSubPair getPreviousSection() const {
if (!SectionStack.empty())
return SectionStack.back().second;
return MCSectionSubPair();
}
/// GetSymbolOrder - Returns an index to represent the order
/// a symbol was emitted in. (zero if we did not emit that symbol)
/// \brief Returns an index to represent the order a symbol was emitted in.
/// (zero if we did not emit that symbol)
unsigned GetSymbolOrder(const MCSymbol *Sym) const {
return SymbolOrdering.lookup(Sym);
}
/// ChangeSection - Update streamer for a new active section.
/// \brief Update streamer for a new active section.
///
/// This is called by PopSection and SwitchSection, if the current
/// section changes.
virtual void ChangeSection(const MCSection *, const MCExpr *);
/// pushSection - Save the current and previous section on the
/// section stack.
/// \brief Save the current and previous section on the section stack.
void PushSection() {
SectionStack.push_back(
std::make_pair(getCurrentSection(), getPreviousSection()));
}
/// popSection - Restore the current and previous section from
/// the section stack. Calls ChangeSection as needed.
/// \brief Restore the current and previous section from the section stack.
/// Calls ChangeSection as needed.
///
/// Returns false if the stack was empty.
bool PopSection() {
@ -344,16 +344,16 @@ public:
return true;
}
/// Set the current section where code is being emitted to @p Section. This
/// Set the current section where code is being emitted to \p Section. This
/// is required to update CurSection.
///
/// This corresponds to assembler directives like .section, .text, etc.
virtual void SwitchSection(const MCSection *Section,
const MCExpr *Subsection = nullptr);
/// SwitchSectionNoChange - Set the current section where code is being
/// emitted to @p Section. This is required to update CurSection. This
/// version does not call ChangeSection.
/// \brief Set the current section where code is being emitted to \p Section.
/// This is required to update CurSection. This version does not call
/// ChangeSection.
void SwitchSectionNoChange(const MCSection *Section,
const MCExpr *Subsection = nullptr) {
assert(Section && "Cannot switch to a null section!");
@ -363,23 +363,23 @@ public:
SectionStack.back().first = MCSectionSubPair(Section, Subsection);
}
/// Create the default sections and set the initial one.
/// \brief Create the default sections and set the initial one.
virtual void InitSections(bool NoExecStack);
MCSymbol *endSection(const MCSection *Section);
/// AssignSection - Sets the symbol's section.
/// \brief Sets the symbol's section.
///
/// Each emitted symbol will be tracked in the ordering table,
/// so we can sort on them later.
void AssignSection(MCSymbol *Symbol, const MCSection *Section);
/// EmitLabel - Emit a label for @p Symbol into the current section.
/// \brief Emit a label for \p Symbol into the current section.
///
/// This corresponds to an assembler statement such as:
/// foo:
///
/// @param Symbol - The symbol to emit. A given symbol should only be
/// \param Symbol - The symbol to emit. A given symbol should only be
/// emitted as a label once, and symbols emitted as a label should never be
/// used in an assignment.
// FIXME: These emission are non-const because we mutate the symbol to
@ -388,25 +388,25 @@ public:
virtual void EmitEHSymAttributes(const MCSymbol *Symbol, MCSymbol *EHSymbol);
/// EmitAssemblerFlag - Note in the output the specified @p Flag.
/// \brief Note in the output the specified \p Flag.
virtual void EmitAssemblerFlag(MCAssemblerFlag Flag);
/// EmitLinkerOptions - Emit the given list @p Options of strings as linker
/// \brief Emit the given list \p Options of strings as linker
/// options into the output.
virtual void EmitLinkerOptions(ArrayRef<std::string> Kind) {}
/// EmitDataRegion - Note in the output the specified region @p Kind.
/// \brief Note in the output the specified region \p Kind.
virtual void EmitDataRegion(MCDataRegionType Kind) {}
/// EmitVersionMin - Specify the MachO minimum deployment target version.
/// \brief Specify the MachO minimum deployment target version.
virtual void EmitVersionMin(MCVersionMinType, unsigned Major, unsigned Minor,
unsigned Update) {}
/// EmitThumbFunc - Note in the output that the specified @p Func is
/// a Thumb mode function (ARM target only).
/// \brief Note in the output that the specified \p Func is a Thumb mode
/// function (ARM target only).
virtual void EmitThumbFunc(MCSymbol *Func);
/// EmitAssignment - Emit an assignment of @p Value to @p Symbol.
/// \brief Emit an assignment of \p Value to \p Symbol.
///
/// This corresponds to an assembler statement such as:
/// symbol = value
@ -415,133 +415,132 @@ public:
/// value in the current context. For the assembly streamer, this prints the
/// binding into the .s file.
///
/// @param Symbol - The symbol being assigned to.
/// @param Value - The value for the symbol.
/// \param Symbol - The symbol being assigned to.
/// \param Value - The value for the symbol.
virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value);
/// EmitWeakReference - Emit an weak reference from @p Alias to @p Symbol.
/// \brief Emit an weak reference from \p Alias to \p Symbol.
///
/// This corresponds to an assembler statement such as:
/// .weakref alias, symbol
///
/// @param Alias - The alias that is being created.
/// @param Symbol - The symbol being aliased.
/// \param Alias - The alias that is being created.
/// \param Symbol - The symbol being aliased.
virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);
/// EmitSymbolAttribute - Add the given @p Attribute to @p Symbol.
/// \brief Add the given \p Attribute to \p Symbol.
virtual bool EmitSymbolAttribute(MCSymbol *Symbol,
MCSymbolAttr Attribute) = 0;
/// EmitSymbolDesc - Set the @p DescValue for the @p Symbol.
/// \brief Set the \p DescValue for the \p Symbol.
///
/// @param Symbol - The symbol to have its n_desc field set.
/// @param DescValue - The value to set into the n_desc field.
/// \param Symbol - The symbol to have its n_desc field set.
/// \param DescValue - The value to set into the n_desc field.
virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue);
/// BeginCOFFSymbolDef - Start emitting COFF symbol definition
/// \brief Start emitting COFF symbol definition
///
/// @param Symbol - The symbol to have its External & Type fields set.
/// \param Symbol - The symbol to have its External & Type fields set.
virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol);
/// EmitCOFFSymbolStorageClass - Emit the storage class of the symbol.
/// \brief Emit the storage class of the symbol.
///
/// @param StorageClass - The storage class the symbol should have.
/// \param StorageClass - The storage class the symbol should have.
virtual void EmitCOFFSymbolStorageClass(int StorageClass);
/// EmitCOFFSymbolType - Emit the type of the symbol.
/// \brief Emit the type of the symbol.
///
/// @param Type - A COFF type identifier (see COFF::SymbolType in X86COFF.h)
/// \param Type - A COFF type identifier (see COFF::SymbolType in X86COFF.h)
virtual void EmitCOFFSymbolType(int Type);
/// EndCOFFSymbolDef - Marks the end of the symbol definition.
/// \brief Marks the end of the symbol definition.
virtual void EndCOFFSymbolDef();
/// EmitCOFFSectionIndex - Emits a COFF section index.
/// \brief Emits a COFF section index.
///
/// @param Symbol - Symbol the section number relocation should point to.
/// \param Symbol - Symbol the section number relocation should point to.
virtual void EmitCOFFSectionIndex(MCSymbol const *Symbol);
/// EmitCOFFSecRel32 - Emits a COFF section relative relocation.
/// \brief Emits a COFF section relative relocation.
///
/// @param Symbol - Symbol the section relative relocation should point to.
/// \param Symbol - Symbol the section relative relocation should point to.
virtual void EmitCOFFSecRel32(MCSymbol const *Symbol);
/// EmitELFSize - Emit an ELF .size directive.
/// \brief Emit an ELF .size directive.
///
/// This corresponds to an assembler statement such as:
/// .size symbol, expression
///
virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value);
/// \brief Emit a Linker Optimization Hint (LOH) directive.
/// \param Args - Arguments of the LOH.
virtual void EmitLOHDirective(MCLOHType Kind, const MCLOHArgs &Args) {}
/// EmitCommonSymbol - Emit a common symbol.
/// \brief Emit a common symbol.
///
/// @param Symbol - The common symbol to emit.
/// @param Size - The size of the common symbol.
/// @param ByteAlignment - The alignment of the symbol if
/// \param Symbol - The common symbol to emit.
/// \param Size - The size of the common symbol.
/// \param ByteAlignment - The alignment of the symbol if
/// non-zero. This must be a power of 2.
virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
unsigned ByteAlignment) = 0;
/// EmitLocalCommonSymbol - Emit a local common (.lcomm) symbol.
/// \brief Emit a local common (.lcomm) symbol.
///
/// @param Symbol - The common symbol to emit.
/// @param Size - The size of the common symbol.
/// @param ByteAlignment - The alignment of the common symbol in bytes.
/// \param Symbol - The common symbol to emit.
/// \param Size - The size of the common symbol.
/// \param ByteAlignment - The alignment of the common symbol in bytes.
virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
unsigned ByteAlignment);
/// EmitZerofill - Emit the zerofill section and an optional symbol.
/// \brief Emit the zerofill section and an optional symbol.
///
/// @param Section - The zerofill section to create and or to put the symbol
/// @param Symbol - The zerofill symbol to emit, if non-NULL.
/// @param Size - The size of the zerofill symbol.
/// @param ByteAlignment - The alignment of the zerofill symbol if
/// \param Section - The zerofill section to create and or to put the symbol
/// \param Symbol - The zerofill symbol to emit, if non-NULL.
/// \param Size - The size of the zerofill symbol.
/// \param ByteAlignment - The alignment of the zerofill symbol if
/// non-zero. This must be a power of 2 on some targets.
virtual void EmitZerofill(const MCSection *Section,
MCSymbol *Symbol = nullptr, uint64_t Size = 0,
unsigned ByteAlignment = 0) = 0;
/// EmitTBSSSymbol - Emit a thread local bss (.tbss) symbol.
/// \brief Emit a thread local bss (.tbss) symbol.
///
/// @param Section - The thread local common section.
/// @param Symbol - The thread local common symbol to emit.
/// @param Size - The size of the symbol.
/// @param ByteAlignment - The alignment of the thread local common symbol
/// \param Section - The thread local common section.
/// \param Symbol - The thread local common symbol to emit.
/// \param Size - The size of the symbol.
/// \param ByteAlignment - The alignment of the thread local common symbol
/// if non-zero. This must be a power of 2 on some targets.
virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
uint64_t Size, unsigned ByteAlignment = 0);
/// @}
/// @name Generating Data
/// \name Generating Data
/// @{
/// EmitBytes - Emit the bytes in \p Data into the output.
/// \brief Emit the bytes in \p Data into the output.
///
/// This is used to implement assembler directives such as .byte, .ascii,
/// etc.
virtual void EmitBytes(StringRef Data);
/// EmitValue - Emit the expression @p Value into the output as a native
/// integer of the given @p Size bytes.
/// \brief Emit the expression \p Value into the output as a native
/// integer of the given \p Size bytes.
///
/// This is used to implement assembler directives such as .word, .quad,
/// etc.
///
/// @param Value - The value to emit.
/// @param Size - The size of the integer (in bytes) to emit. This must
/// \param Value - The value to emit.
/// \param Size - The size of the integer (in bytes) to emit. This must
/// match a native machine width.
/// @param Loc - The location of the expression for error reporting.
/// \param Loc - The location of the expression for error reporting.
virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
const SMLoc &Loc = SMLoc());
void EmitValue(const MCExpr *Value, unsigned Size,
const SMLoc &Loc = SMLoc());
/// EmitIntValue - Special case of EmitValue that avoids the client having
/// \brief Special case of EmitValue that avoids the client having
/// to pass in a MCExpr for constant integers.
virtual void EmitIntValue(uint64_t Value, unsigned Size);
@ -549,107 +548,105 @@ public:
virtual void EmitSLEB128Value(const MCExpr *Value);
/// EmitULEB128Value - Special case of EmitULEB128Value that avoids the
/// client having to pass in a MCExpr for constant integers.
/// \brief Special case of EmitULEB128Value that avoids the client having to
/// pass in a MCExpr for constant integers.
void EmitULEB128IntValue(uint64_t Value, unsigned Padding = 0);
/// EmitSLEB128Value - Special case of EmitSLEB128Value that avoids the
/// client having to pass in a MCExpr for constant integers.
/// \brief Special case of EmitSLEB128Value that avoids the client having to
/// pass in a MCExpr for constant integers.
void EmitSLEB128IntValue(int64_t Value);
/// EmitSymbolValue - Special case of EmitValue that avoids the client
/// having to pass in a MCExpr for MCSymbols.
/// \brief Special case of EmitValue that avoids the client having to pass in
/// a MCExpr for MCSymbols.
void EmitSymbolValue(const MCSymbol *Sym, unsigned Size,
bool IsSectionRelative = false);
/// EmitGPRel64Value - Emit the expression @p Value into the output as a
/// gprel64 (64-bit GP relative) value.
/// \brief Emit the expression \p Value into the output as a gprel64 (64-bit
/// GP relative) value.
///
/// This is used to implement assembler directives such as .gpdword on
/// targets that support them.
virtual void EmitGPRel64Value(const MCExpr *Value);
/// EmitGPRel32Value - Emit the expression @p Value into the output as a
/// gprel32 (32-bit GP relative) value.
/// \brief Emit the expression \p Value into the output as a gprel32 (32-bit
/// GP relative) value.
///
/// This is used to implement assembler directives such as .gprel32 on
/// targets that support them.
virtual void EmitGPRel32Value(const MCExpr *Value);
/// EmitFill - Emit NumBytes bytes worth of the value specified by
/// FillValue. This implements directives such as '.space'.
/// \brief Emit NumBytes bytes worth of the value specified by FillValue.
/// This implements directives such as '.space'.
virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue);
/// \brief Emit NumBytes worth of zeros.
/// This function properly handles data in virtual sections.
virtual void EmitZeros(uint64_t NumBytes);
/// EmitValueToAlignment - Emit some number of copies of @p Value until
/// the byte alignment @p ByteAlignment is reached.
/// \brief Emit some number of copies of \p Value until the byte alignment \p
/// ByteAlignment is reached.
///
/// If the number of bytes need to emit for the alignment is not a multiple
/// of @p ValueSize, then the contents of the emitted fill bytes is
/// of \p ValueSize, then the contents of the emitted fill bytes is
/// undefined.
///
/// This used to implement the .align assembler directive.
///
/// @param ByteAlignment - The alignment to reach. This must be a power of
/// \param ByteAlignment - The alignment to reach. This must be a power of
/// two on some targets.
/// @param Value - The value to use when filling bytes.
/// @param ValueSize - The size of the integer (in bytes) to emit for
/// @p Value. This must match a native machine width.
/// @param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. If
/// \param Value - The value to use when filling bytes.
/// \param ValueSize - The size of the integer (in bytes) to emit for
/// \p Value. This must match a native machine width.
/// \param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. If
/// the alignment cannot be reached in this many bytes, no bytes are
/// emitted.
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0,
unsigned ValueSize = 1,
unsigned MaxBytesToEmit = 0);
/// EmitCodeAlignment - Emit nops until the byte alignment @p ByteAlignment
/// is reached.
/// \brief Emit nops until the byte alignment \p ByteAlignment is reached.
///
/// This used to align code where the alignment bytes may be executed. This
/// can emit different bytes for different sizes to optimize execution.
///
/// @param ByteAlignment - The alignment to reach. This must be a power of
/// \param ByteAlignment - The alignment to reach. This must be a power of
/// two on some targets.
/// @param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. If
/// \param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. If
/// the alignment cannot be reached in this many bytes, no bytes are
/// emitted.
virtual void EmitCodeAlignment(unsigned ByteAlignment,
unsigned MaxBytesToEmit = 0);
/// EmitValueToOffset - Emit some number of copies of @p Value until the
/// byte offset @p Offset is reached.
/// \brief Emit some number of copies of \p Value until the byte offset \p
/// Offset is reached.
///
/// This is used to implement assembler directives such as .org.
///
/// @param Offset - The offset to reach. This may be an expression, but the
/// \param Offset - The offset to reach. This may be an expression, but the
/// expression must be associated with the current section.
/// @param Value - The value to use when filling bytes.
/// @return false on success, true if the offset was invalid.
/// \param Value - The value to use when filling bytes.
/// \return false on success, true if the offset was invalid.
virtual bool EmitValueToOffset(const MCExpr *Offset,
unsigned char Value = 0);
/// @}
/// EmitFileDirective - Switch to a new logical file. This is used to
/// implement the '.file "foo.c"' assembler directive.
/// \brief Switch to a new logical file. This is used to implement the '.file
/// "foo.c"' assembler directive.
virtual void EmitFileDirective(StringRef Filename);
/// Emit the "identifiers" directive. This implements the
/// \brief Emit the "identifiers" directive. This implements the
/// '.ident "version foo"' assembler directive.
virtual void EmitIdent(StringRef IdentString) {}
/// EmitDwarfFileDirective - Associate a filename with a specified logical
/// file number. This implements the DWARF2 '.file 4 "foo.c"' assembler
/// directive.
/// \brief Associate a filename with a specified logical file number. This
/// implements the DWARF2 '.file 4 "foo.c"' assembler directive.
virtual unsigned EmitDwarfFileDirective(unsigned FileNo, StringRef Directory,
StringRef Filename,
unsigned CUID = 0);
/// EmitDwarfLocDirective - This implements the DWARF2
// '.loc fileno lineno ...' assembler directive.
/// \brief This implements the DWARF2 '.loc fileno lineno ...' assembler
/// directive.
virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line,
unsigned Column, unsigned Flags,
unsigned Isa, unsigned Discriminator,
@ -692,8 +689,7 @@ public:
virtual void EmitWinEHHandler(const MCSymbol *Sym, bool Unwind, bool Except);
virtual void EmitWinEHHandlerData();
/// EmitInstruction - Emit the given @p Instruction into the current
/// section.
/// \brief Emit the given \p Instruction into the current section.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI);
/// \brief Set the bundle alignment mode from now on in the section.
@ -710,17 +706,17 @@ public:
/// \brief Ends a bundle-locked group.
virtual void EmitBundleUnlock();
/// EmitRawText - If this file is backed by a assembly streamer, this dumps
/// the specified string in the output .s file. This capability is
/// indicated by the hasRawTextSupport() predicate. By default this aborts.
/// \brief If this file is backed by a assembly streamer, this dumps the
/// specified string in the output .s file. This capability is indicated by
/// the hasRawTextSupport() predicate. By default this aborts.
void EmitRawText(const Twine &String);
/// Flush - Causes any cached state to be written out.
/// \brief Causes any cached state to be written out.
virtual void Flush() {}
/// FinishImpl - Streamer specific finalization.
/// \brief Streamer specific finalization.
virtual void FinishImpl();
/// Finish - Finish emission of machine code.
/// \brief Finish emission of machine code.
void Finish();
virtual bool mayHaveInstructions() const { return true; }

6
llvm/include/llvm/MC/MCSymbol.h
View File

@ -80,7 +80,7 @@ namespace llvm {
/// getName - Get the symbol name.
StringRef getName() const { return Name; }
/// @name Accessors
/// \name Accessors
/// @{
/// isTemporary - Check if this is an assembler temporary symbol.
@ -104,7 +104,7 @@ namespace llvm {
}
/// @}
/// @name Associated Sections
/// \name Associated Sections
/// @{
/// isDefined - Check if this symbol is defined (i.e., it has an address).
@ -149,7 +149,7 @@ namespace llvm {
}
/// @}
/// @name Variable Symbols
/// \name Variable Symbols
/// @{
/// isVariable - Check if this is a variable symbol.

16
llvm/include/llvm/MC/MCSymbolizer.h
View File

@ -59,14 +59,14 @@ public:
/// represent this immediate in a more understandable way, for instance as a
/// symbol or an offset from a symbol. Relocations can also be used to enrich
/// the symbolic expression.
/// @param Inst - The MCInst where to insert the symbolic operand.
/// @param cStream - Stream to print comments and annotations on.
/// @param Value - Operand value, pc-adjusted by the caller if necessary.
/// @param Address - Load address of the instruction.
/// @param IsBranch - Is the instruction a branch?
/// @param Offset - Byte offset of the operand inside the inst.
/// @param InstSize - Size of the instruction in bytes.
/// @return Whether a symbolic operand was added.
/// \param Inst - The MCInst where to insert the symbolic operand.
/// \param cStream - Stream to print comments and annotations on.
/// \param Value - Operand value, pc-adjusted by the caller if necessary.
/// \param Address - Load address of the instruction.
/// \param IsBranch - Is the instruction a branch?
/// \param Offset - Byte offset of the operand inside the inst.
/// \param InstSize - Size of the instruction in bytes.
/// \return Whether a symbolic operand was added.
virtual bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
int64_t Value, uint64_t Address,
bool IsBranch, uint64_t Offset,

15
llvm/include/llvm/MC/MCValue.h
View File

@ -23,10 +23,11 @@ namespace llvm {
class MCAsmInfo;
class raw_ostream;
/// MCValue - This represents an "assembler immediate". In its most
/// general form, this can hold ":Kind:(SymbolA - SymbolB + imm64)".
/// Not all targets supports relocations of this general form, but we
/// need to represent this anyway.
/// \brief This represents an "assembler immediate".
///
/// In its most general form, this can hold ":Kind:(SymbolA - SymbolB +
/// imm64)". Not all targets supports relocations of this general form, but we
/// need to represent this anyway.
///
/// In general both SymbolA and SymbolB will also have a modifier
/// analogous to the top-level Kind. Current targets are not expected
@ -51,13 +52,13 @@ public:
const MCSymbolRefExpr *getSymB() const { return SymB; }
uint32_t getRefKind() const { return RefKind; }
/// isAbsolute - Is this an absolute (as opposed to relocatable) value.
/// \brief Is this an absolute (as opposed to relocatable) value.
bool isAbsolute() const { return !SymA && !SymB; }
/// print - Print the value to the stream \p OS.
/// \brief Print the value to the stream \p OS.
void print(raw_ostream &OS) const;
/// dump - Print the value to stderr.
/// \brief Print the value to stderr.
void dump() const;
MCSymbolRefExpr::VariantKind getAccessVariant() const;