forked from OSchip/llvm-project
[x86] add tests for potential vector narrowing optimization (PR32790)
llvm-svn: 302910
This commit is contained in:
Sanjay Patel
parent
cc7257c200
commit
ae362303fd
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ
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; AVX1 has support for 256-bit bitwise logic because the FP variants were included.
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; If using those ops requires extra insert/extract though, it's probably not worth it.
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define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
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; SSE-LABEL: PR32790:
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; SSE: # BB#0:
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; SSE-NEXT: paddd %xmm2, %xmm0
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; SSE-NEXT: paddd %xmm3, %xmm1
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; SSE-NEXT: pand %xmm5, %xmm1
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; SSE-NEXT: pand %xmm4, %xmm0
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; SSE-NEXT: psubd %xmm6, %xmm0
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; SSE-NEXT: psubd %xmm7, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: PR32790:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
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; AVX1-NEXT: vpaddd %xmm4, %xmm5, %xmm4
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
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; AVX1-NEXT: vpsubd %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR32790:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vpsubd %ymm3, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: PR32790:
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; AVX512: # BB#0:
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; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: vpand %ymm2, %ymm0, %ymm0
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; AVX512-NEXT: vpsubd %ymm3, %ymm0, %ymm0
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; AVX512-NEXT: retq
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%add = add <8 x i32> %a, %b
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%and = and <8 x i32> %add, %c
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%sub = sub <8 x i32> %and, %d
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ret <8 x i32> %sub
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}
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; In a more extreme case, even the later AVX targets should avoid extract/insert just
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; because 256-bit ops are supported.
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define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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; SSE-LABEL: do_not_use_256bit_op:
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; SSE: # BB#0:
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; SSE-NEXT: pand %xmm3, %xmm1
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: do_not_use_256bit_op:
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; AVX1: # BB#0:
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; AVX1-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
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; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm1
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: do_not_use_256bit_op:
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; AVX2: # BB#0:
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; AVX2-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
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; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
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; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm1
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: do_not_use_256bit_op:
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; AVX512: # BB#0:
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; AVX512-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def>
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; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def>
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; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm1
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; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%concat1 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%concat2 = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%and = and <8 x i32> %concat1, %concat2
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%extract1 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%extract2 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%sub = sub <4 x i32> %extract1, %extract2
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ret <4 x i32> %sub
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}
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