forked from OSchip/llvm-project
Add support for Thumb load/stores with negative offsets.
rdar://10412592 llvm-svn: 144565
This commit is contained in:
Chad Rosier
parent
731607fab2
commit
adfd200bcb
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@ -870,12 +870,17 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) {
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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if (!useAM3)
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if (!useAM3) {
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// Integer loads/stores handle 12-bit offsets.
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needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
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else
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// Handle negative offsets.
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if (isThumb2)
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needsLowering = !(needsLowering && Subtarget->hasV6T2Ops() &&
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Addr.Offset < 0 && Addr.Offset > -256);
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} else {
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// ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
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needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
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}
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break;
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case MVT::f32:
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case MVT::f64:
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@ -967,24 +972,42 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
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default: return false;
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case MVT::i1:
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case MVT::i8:
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if (isZExt) {
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Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
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if (isThumb2) {
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if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
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Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
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else
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Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
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} else {
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Opc = isThumb2 ? ARM::t2LDRSBi12 : ARM::LDRSB;
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if (!isThumb2) useAM3 = true;
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if (isZExt) {
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Opc = ARM::LDRBi12;
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} else {
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Opc = ARM::LDRSB;
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useAM3 = true;
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}
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}
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::i16:
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if (isZExt)
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Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
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if (isThumb2) {
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if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
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Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
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else
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Opc = isThumb2 ? ARM::t2LDRSHi12 : ARM::LDRSH;
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if (!isThumb2) useAM3 = true;
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Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
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} else {
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Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
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useAM3 = true;
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}
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::i32:
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Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
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if (isThumb2) {
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if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
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Opc = ARM::t2LDRi8;
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else
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Opc = ARM::t2LDRi12;
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} else {
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Opc = ARM::LDRi12;
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}
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::f32:
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@ -1045,14 +1068,35 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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SrcReg = Res;
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} // Fallthrough here.
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case MVT::i8:
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StrOpc = isThumb2 ? ARM::t2STRBi12 : ARM::STRBi12;
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if (isThumb2) {
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if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
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StrOpc = ARM::t2STRBi8;
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else
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StrOpc = ARM::t2STRBi12;
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} else {
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StrOpc = ARM::STRBi12;
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}
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break;
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case MVT::i16:
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StrOpc = isThumb2 ? ARM::t2STRHi12 : ARM::STRH;
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if (!isThumb2) useAM3 = true;
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if (isThumb2) {
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if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
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StrOpc = ARM::t2STRHi8;
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else
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StrOpc = ARM::t2STRHi12;
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} else {
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StrOpc = ARM::STRH;
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useAM3 = true;
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}
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break;
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case MVT::i32:
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StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
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if (isThumb2) {
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if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
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StrOpc = ARM::t2STRi8;
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else
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StrOpc = ARM::t2STRi12;
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} else {
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StrOpc = ARM::STRi12;
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}
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break;
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case MVT::f32:
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if (!Subtarget->hasVFP2()) return false;
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@ -0,0 +1,168 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
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define i32 @t1(i32* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t1
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%add.ptr = getelementptr inbounds i32* %ptr, i32 -1
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%0 = load i32* %add.ptr, align 4, !tbaa !0
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; THUMB: ldr r{{[0-9]}}, [r0, #-4]
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ret i32 %0
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}
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define i32 @t2(i32* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t2
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%add.ptr = getelementptr inbounds i32* %ptr, i32 -63
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%0 = load i32* %add.ptr, align 4, !tbaa !0
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; THUMB: ldr r{{[0-9]}}, [r0, #-252]
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ret i32 %0
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}
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define i32 @t3(i32* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t3
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%add.ptr = getelementptr inbounds i32* %ptr, i32 -64
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%0 = load i32* %add.ptr, align 4, !tbaa !0
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; THUMB: ldr r{{[0-9]}}, [r0]
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ret i32 %0
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}
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define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t4
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%add.ptr = getelementptr inbounds i16* %ptr, i32 -1
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%0 = load i16* %add.ptr, align 2, !tbaa !3
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; THUMB: ldrh r{{[0-9]}}, [r0, #-2]
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ret i16 %0
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}
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define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t5
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%add.ptr = getelementptr inbounds i16* %ptr, i32 -127
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%0 = load i16* %add.ptr, align 2, !tbaa !3
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; THUMB: ldrh r{{[0-9]}}, [r0, #-254]
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ret i16 %0
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}
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define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t6
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%add.ptr = getelementptr inbounds i16* %ptr, i32 -128
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%0 = load i16* %add.ptr, align 2, !tbaa !3
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; THUMB: ldrh r{{[0-9]}}, [r0]
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ret i16 %0
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}
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define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t7
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%add.ptr = getelementptr inbounds i8* %ptr, i32 -1
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%0 = load i8* %add.ptr, align 1, !tbaa !1
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; THUMB: ldrb r{{[0-9]}}, [r0, #-1]
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ret i8 %0
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}
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define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t8
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%add.ptr = getelementptr inbounds i8* %ptr, i32 -255
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%0 = load i8* %add.ptr, align 1, !tbaa !1
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; THUMB: ldrb r{{[0-9]}}, [r0, #-255]
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ret i8 %0
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}
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define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly {
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entry:
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; THUMB: t9
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%add.ptr = getelementptr inbounds i8* %ptr, i32 -256
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%0 = load i8* %add.ptr, align 1, !tbaa !1
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; THUMB: ldrb r{{[0-9]}}, [r0]
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ret i8 %0
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}
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define void @t10(i32* nocapture %ptr) nounwind {
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entry:
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; THUMB: t10
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%add.ptr = getelementptr inbounds i32* %ptr, i32 -1
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store i32 0, i32* %add.ptr, align 4, !tbaa !0
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; THUMB: str r{{[0-9]}}, [r0, #-4]
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ret void
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}
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define void @t11(i32* nocapture %ptr) nounwind {
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entry:
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; THUMB: t11
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%add.ptr = getelementptr inbounds i32* %ptr, i32 -63
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store i32 0, i32* %add.ptr, align 4, !tbaa !0
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; THUMB: str r{{[0-9]}}, [r0, #-252]
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ret void
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}
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define void @t12(i32* nocapture %ptr) nounwind {
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entry:
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; THUMB: t12
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%add.ptr = getelementptr inbounds i32* %ptr, i32 -64
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store i32 0, i32* %add.ptr, align 4, !tbaa !0
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; THUMB: str r{{[0-9]}}, [r0]
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ret void
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}
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define void @t13(i16* nocapture %ptr) nounwind {
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entry:
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; THUMB: t13
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%add.ptr = getelementptr inbounds i16* %ptr, i32 -1
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store i16 0, i16* %add.ptr, align 2, !tbaa !3
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; THUMB: strh r{{[0-9]}}, [r0, #-2]
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ret void
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}
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define void @t14(i16* nocapture %ptr) nounwind {
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entry:
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; THUMB: t14
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%add.ptr = getelementptr inbounds i16* %ptr, i32 -127
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store i16 0, i16* %add.ptr, align 2, !tbaa !3
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; THUMB: strh r{{[0-9]}}, [r0, #-254]
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ret void
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}
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define void @t15(i16* nocapture %ptr) nounwind {
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entry:
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; THUMB: t15
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%add.ptr = getelementptr inbounds i16* %ptr, i32 -128
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store i16 0, i16* %add.ptr, align 2, !tbaa !3
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; THUMB: strh r{{[0-9]}}, [r0]
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ret void
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}
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define void @t16(i8* nocapture %ptr) nounwind {
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entry:
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; THUMB: t16
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%add.ptr = getelementptr inbounds i8* %ptr, i32 -1
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store i8 0, i8* %add.ptr, align 1, !tbaa !1
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; THUMB: strb r{{[0-9]}}, [r0, #-1]
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ret void
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}
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define void @t17(i8* nocapture %ptr) nounwind {
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entry:
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; THUMB: t17
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%add.ptr = getelementptr inbounds i8* %ptr, i32 -255
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store i8 0, i8* %add.ptr, align 1, !tbaa !1
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; THUMB: strb r{{[0-9]}}, [r0, #-255]
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ret void
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}
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define void @t18(i8* nocapture %ptr) nounwind {
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entry:
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; THUMB: t18
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%add.ptr = getelementptr inbounds i8* %ptr, i32 -256
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store i8 0, i8* %add.ptr, align 1, !tbaa !1
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; THUMB: strb r{{[0-9]}}, [r0]
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ret void
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}
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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!3 = metadata !{metadata !"short", metadata !1}
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