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[AArch64] Add test case from D127354

This commit is contained in:
Simon Pilgrim 2022-06-15 12:19:34 +01:00
parent 8bc0bb9564
commit adfcdb0d0d
1 changed files with 22 additions and 0 deletions
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22
llvm/test/CodeGen/AArch64/add-negative.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
; FIXME: D127354
define <8 x i16> @add_to_sub(<8 x i16> %0, <8 x i16> %1) {
; CHECK-LABEL: add_to_sub:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: movi v3.8h, #1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: cmhi v1.8h, v2.8h, v1.8h
; CHECK-NEXT: cmhi v0.8h, v2.8h, v0.8h
; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
; CHECK-NEXT: add v0.8h, v1.8h, v0.8h
; CHECK-NEXT: ret
%3 = icmp ult <8 x i16> %0, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
%4 = sext <8 x i1> %3 to <8 x i16>
%5 = icmp ult <8 x i16> %1, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
%6 = zext <8 x i1> %5 to <8 x i16>
%7 = add nsw <8 x i16> %6, %4
ret <8 x i16> %7
}