forked from OSchip/llvm-project
[ARM] Describe defs/uses of VLLDM and VLSTM
The VLLDM and VLSTM instructions are incompletely specified. They (potentially) write (or read, respectively) registers Q0-Q7, VPR, and FPSCR, but the compiler is unaware of it. In the new test case `cmse-vlldm-no-reorder.ll` case the compiler missed an anti-dependency and reordered a `VLLDM` ahead of the instruction, which stashed the return value from the non-secure call, effectively clobbering said value. This test case does not fail with upstream LLVM, because of scheduling differences and I couldn't find a test case for the VLSTM either. Differential Revision: https://reviews.llvm.org/D81586
This commit is contained in:
Momchil Velikov
parent
510796d1a7
commit
adf7973fd3
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@ -85,12 +85,15 @@ namespace {
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const BitVector &ClearRegs);
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void CMSESaveClearFPRegs(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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const LivePhysRegs &LiveRegs,
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SmallVectorImpl<unsigned> &AvailableRegs);
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void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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const LivePhysRegs &LiveRegs,
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SmallVectorImpl<unsigned> &ScratchRegs);
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void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc &DL);
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MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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const LivePhysRegs &LiveRegs);
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void CMSERestoreFPRegs(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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SmallVectorImpl<unsigned> &AvailableRegs);
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@ -1202,17 +1205,17 @@ ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB,
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void ARMExpandPseudo::CMSESaveClearFPRegs(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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SmallVectorImpl<unsigned> &ScratchRegs) {
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const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
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if (STI->hasV8_1MMainlineOps())
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CMSESaveClearFPRegsV81(MBB, MBBI, DL);
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CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
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else
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CMSESaveClearFPRegsV8(MBB, MBBI, DL, ScratchRegs);
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CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs);
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}
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// Save and clear FP registers if present
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void ARMExpandPseudo::CMSESaveClearFPRegsV8(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
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SmallVectorImpl<unsigned> &ScratchRegs) {
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const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
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if (!STI->hasFPRegs())
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return;
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@ -1271,7 +1274,11 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
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// Lazy store all fp registers to the stack
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MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
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.addReg(ARM::SP)
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.add(predOps(ARMCC::AL));
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.add(predOps(ARMCC::AL));
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for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
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ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
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VLSTM.addReg(R, RegState::Implicit |
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(LiveRegs.contains(R) ? 0 : RegState::Undef));
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// Restore all arguments
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for (const auto &Regs : ClearedFPRegs) {
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@ -1343,7 +1350,8 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV8(
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void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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DebugLoc &DL) {
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DebugLoc &DL,
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const LivePhysRegs &LiveRegs) {
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BitVector ClearRegs(32, true);
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bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs);
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@ -1358,9 +1366,13 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
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.add(predOps(ARMCC::AL));
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// Lazy store all FP registers to the stack
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BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
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.addReg(ARM::SP)
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.add(predOps(ARMCC::AL));
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MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
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.addReg(ARM::SP)
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.add(predOps(ARMCC::AL));
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for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
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ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
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VLSTM.addReg(R, RegState::Implicit |
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(LiveRegs.contains(R) ? 0 : RegState::Undef));
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} else {
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// Push all the callee-saved registers (s16-s31).
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MachineInstrBuilder VPUSH =
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@ -1754,13 +1766,15 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
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static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, int JumpReg,
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bool Thumb1Only) {
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const LivePhysRegs &LiveRegs, bool Thumb1Only) {
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const DebugLoc &DL = MBBI->getDebugLoc();
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if (Thumb1Only) { // push Lo and Hi regs separately
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MachineInstrBuilder PushMIB =
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BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
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for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg)
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PushMIB.addReg(Reg, Reg != JumpReg ? RegState::Undef : 0);
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for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
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PushMIB.addReg(
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Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef);
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}
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// Thumb1 can only tPUSH low regs, so we copy the high regs to the low
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// regs that we just saved and push the low regs again, taking care to
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@ -1773,7 +1787,7 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
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if (JumpReg == LoReg)
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continue;
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BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
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.addReg(HiReg, RegState::Undef)
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.addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef)
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.add(predOps(ARMCC::AL));
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--HiReg;
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}
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@ -1791,19 +1805,21 @@ static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
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if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) {
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int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4;
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BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
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.addReg(ARM::R8)
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.addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef)
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.add(predOps(ARMCC::AL));
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BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH))
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.add(predOps(ARMCC::AL))
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.addReg(LoReg);
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.addReg(LoReg, RegState::Kill);
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}
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} else { // push Lo and Hi registers with a single instruction
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MachineInstrBuilder PushMIB =
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BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
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.addReg(ARM::SP)
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.add(predOps(ARMCC::AL));
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for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg)
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PushMIB.addReg(Reg, Reg != JumpReg ? RegState::Undef : 0);
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for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
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PushMIB.addReg(
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Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef);
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}
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}
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}
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@ -1934,7 +1950,18 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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case ARM::tBLXNS_CALL: {
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DebugLoc DL = MBBI->getDebugLoc();
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unsigned JumpReg = MBBI->getOperand(0).getReg();
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CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg,
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// Figure out which registers are live at the point immediately before the
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// call. When we indiscriminately push a set of registers, the live
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// registers are added as ordinary use operands, whereas dead registers
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// are "undef".
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LivePhysRegs LiveRegs(*TRI);
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LiveRegs.addLiveOuts(MBB);
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for (const MachineInstr &MI : make_range(MBB.rbegin(), MBBI.getReverse()))
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LiveRegs.stepBackward(MI);
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LiveRegs.stepBackward(*MBBI);
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CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs,
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AFI->isThumb1OnlyFunction());
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SmallVector<unsigned, 16> ClearRegs;
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@ -1971,7 +1998,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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.add(predOps(ARMCC::AL));
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}
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CMSESaveClearFPRegs(MBB, MBBI, DL,
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CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs,
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ClearRegs); // save+clear FP regs with ClearRegs
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CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg);
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@ -287,7 +287,6 @@ def : MnemonicAlias<"vstm", "vstmia">;
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//===----------------------------------------------------------------------===//
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// Lazy load / store multiple Instructions
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//
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let mayLoad = 1 in
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def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
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NoItinerary, "vlldm${p}\t$Rn", "", []>,
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Requires<[HasV8MMainline, Has8MSecExt]> {
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@ -298,9 +297,9 @@ def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
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let Inst{15-12} = 0;
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let Inst{7-0} = 0;
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let mayLoad = 1;
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let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV];
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}
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let mayStore = 1 in
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def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
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NoItinerary, "vlstm${p}\t$Rn", "", []>,
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Requires<[HasV8MMainline, Has8MSecExt]> {
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@ -0,0 +1,21 @@
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; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 --float-abi=hard %s -o - | \
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; RUN: FileCheck %s
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@g = hidden local_unnamed_addr global float (...)* null, align 4
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@a = hidden local_unnamed_addr global float 0.000000e+00, align 4
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define hidden void @f() local_unnamed_addr #0 {
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entry:
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%0 = load float ()*, float ()** bitcast (float (...)** @g to float ()**), align 4
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%call = tail call nnan ninf nsz float %0() #1
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store float %call, float* @a, align 4
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ret void
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}
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; CHECK: blxns r{{[0-9]+}}
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; CHECK: vmov r[[T:[0-9]+]], s0
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; CHECK: vlldm sp
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; CHECK: vmov s0, r[[T]]
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attributes #0 = { nounwind }
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attributes #1 = { nounwind "cmse_nonsecure_call" }
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@ -0,0 +1,112 @@
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# RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 --float-abi=hard --run-pass=arm-pseudo %s -o - | \
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# RUN: FileCheck %s
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--- |
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; ModuleID = 'cmse-vlldm-no-reorder.ll'
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source_filename = "cmse-vlldm-no-reorder.ll"
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8m.main"
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@g = hidden local_unnamed_addr global float (...)* null, align 4
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@a = hidden local_unnamed_addr global float 0.000000e+00, align 4
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; Function Attrs: nounwind
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define hidden void @f() local_unnamed_addr #0 {
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entry:
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%0 = load float ()*, float ()** bitcast (float (...)** @g to float ()**), align 4
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%call = tail call nnan ninf nsz float %0() #2
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store float %call, float* @a, align 4
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ret void
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}
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { nounwind "target-cpu"="cortex-m33" }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind "cmse_nonsecure_call" }
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...
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---
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name: f
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $r7, $lr
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$sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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renamable $r0 = t2MOVi32imm @g
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renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from `float ()** bitcast (float (...)** @g to float ()**)`)
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tBLXNS_CALL killed renamable $r0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s0
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renamable $r0 = t2MOVi32imm @a
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VSTRS killed renamable $s0, killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4 into @a)
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$sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc
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...
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# CHECK-LABEL: bb.0.entry:
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# CHECK: $sp = t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, $r4, $r5, $r6, undef $r7, $r8, $r9, $r10, $r11
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# CHECK-NEXT: $r0 = t2BICri $r0, 1, 14 /* CC::al */, $noreg, $noreg
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# CHECK-NEXT: $sp = tSUBspi $sp, 34, 14 /* CC::al */, $noreg
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# CHECK-NEXT: VLSTM $sp, 14 /* CC::al */, $noreg, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $q0, implicit undef $q1, implicit undef $q2, implicit undef $q3, implicit undef $q4, implicit undef $q5, implicit undef $q6, implicit undef $q7
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# CHECK-NEXT: $r1 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r7 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r9 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r11 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: t2MSR_M 3072, $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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# CHECK-NEXT: tBLXNSr 14 /* CC::al */, $noreg, killed $r0, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s0
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# CHECK-NEXT: $r12 = VMOVRS $s0, 14 /* CC::al */, $noreg
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# CHECK-NEXT: VLLDM $sp, 14 /* CC::al */, $noreg, implicit-def $q0, implicit-def $q1, implicit-def $q2, implicit-def $q3, implicit-def $q4, implicit-def $q5, implicit-def $q6, implicit-def $q7, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv
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# CHECK-NEXT: $s0 = VMOVSR $r12, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $sp = tADDspi $sp, 34, 14 /* CC::al */, $noreg
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# CHECK-NEXT: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11
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@ -62,7 +62,7 @@ body: |
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$sp = tSUBspi $sp, 34, 14, $noreg
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VLSTM $sp, 14, $noreg
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tBLXNSr 14, $noreg, killed $r4, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp
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VLLDM $sp, 14, $noreg
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VLLDM $sp, 14, $noreg, implicit-def $q0, implicit-def $q1, implicit-def $q2, implicit-def $q3, implicit-def $q4, implicit-def $q5, implicit-def $q6, implicit-def $q7, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv
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$sp = tADDspi $sp, 34, 14, $noreg
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$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11
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$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
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Reference in New Issue