forked from OSchip/llvm-project
builtins: Add ARM Thumb1 implementation for uidiv and uidivmod
Summary: The current uidiv supports archs without clz. However, the asm is for thumb2/arm. For uidivmod, the existing code calls the C version of uidivmodsi4, which then calls uidiv. The extra push/pop/bl makes it less efficient. Reviewers: jmolloy, jroelofs, joerg, compnerd, rengolin Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D27309 llvm-svn: 288710
This commit is contained in:
Weiming Zhao
parent
6ad7b9f837
commit
adf4258f50
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@ -23,6 +23,20 @@
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.syntax unified
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.p2align 2
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DEFINE_COMPILERRT_FUNCTION(__aeabi_uidivmod)
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#if __ARM_ARCH_ISA_THUMB == 1
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cmp r0, r1
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bcc LOCAL_LABEL(case_denom_larger)
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push {r0, r1, lr}
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bl SYMBOL_NAME(__aeabi_uidiv)
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pop {r1, r2, r3}
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muls r2, r2, r0 // r2 = quot * denom
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subs r1, r1, r2
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JMP (r3)
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LOCAL_LABEL(case_denom_larger):
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movs r1, r0
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movs r0, #0
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JMP (lr)
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#else
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push { lr }
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sub sp, sp, #4
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mov r2, sp
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@ -35,6 +49,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_uidivmod)
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ldr r1, [sp]
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add sp, sp, #4
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pop { pc }
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#endif
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END_COMPILERRT_FUNCTION(__aeabi_uidivmod)
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NO_EXEC_STACK_DIRECTIVE
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@ -40,12 +40,26 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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#else
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cmp r1, #1
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bcc LOCAL_LABEL(divby0)
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#if __ARM_ARCH_ISA_THUMB == 1
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bne LOCAL_LABEL(num_neq_denom)
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JMP(lr)
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LOCAL_LABEL(num_neq_denom):
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#else
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IT(eq)
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JMPc(lr, eq)
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#endif
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cmp r0, r1
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#if __ARM_ARCH_ISA_THUMB == 1
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bhs LOCAL_LABEL(num_ge_denom)
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movs r0, #0
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JMP(lr)
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LOCAL_LABEL(num_ge_denom):
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#else
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ITT(cc)
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movcc r0, #0
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JMPc(lr, cc)
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#endif
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/*
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* Implement division using binary long division algorithm.
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*
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@ -62,7 +76,7 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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* that (r0 << shift) < 2 * r1. The quotient is stored in r3.
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*/
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# ifdef __ARM_FEATURE_CLZ
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# if defined(__ARM_FEATURE_CLZ)
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clz ip, r0
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clz r3, r1
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/* r0 >= r1 implies clz(r0) <= clz(r1), so ip <= r3. */
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@ -77,49 +91,128 @@ DEFINE_COMPILERRT_FUNCTION(__udivsi3)
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sub ip, ip, r3, lsl #3
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mov r3, #0
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bx ip
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# else
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# else /* No CLZ Feature */
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# if __ARM_ARCH_ISA_THUMB == 2
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# error THUMB mode requires CLZ or UDIV
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# endif
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# if __ARM_ARCH_ISA_THUMB == 1
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# define BLOCK_SIZE 10
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# else
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# define BLOCK_SIZE 12
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# endif
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mov r2, r0
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# if __ARM_ARCH_ISA_THUMB == 1
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mov ip, r0
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adr r0, LOCAL_LABEL(div0block)
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adds r0, #1
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# else
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adr ip, LOCAL_LABEL(div0block)
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lsr r3, r2, #16
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# endif
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lsrs r3, r2, #16
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cmp r3, r1
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# if __ARM_ARCH_ISA_THUMB == 1
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blo LOCAL_LABEL(skip_16)
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movs r2, r3
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subs r0, r0, #(16 * BLOCK_SIZE)
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LOCAL_LABEL(skip_16):
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# else
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movhs r2, r3
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subhs ip, ip, #(16 * 12)
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subhs ip, ip, #(16 * BLOCK_SIZE)
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# endif
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lsr r3, r2, #8
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lsrs r3, r2, #8
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cmp r3, r1
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# if __ARM_ARCH_ISA_THUMB == 1
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blo LOCAL_LABEL(skip_8)
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movs r2, r3
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subs r0, r0, #(8 * BLOCK_SIZE)
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LOCAL_LABEL(skip_8):
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# else
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movhs r2, r3
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subhs ip, ip, #(8 * 12)
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subhs ip, ip, #(8 * BLOCK_SIZE)
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# endif
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lsr r3, r2, #4
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lsrs r3, r2, #4
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cmp r3, r1
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# if __ARM_ARCH_ISA_THUMB == 1
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blo LOCAL_LABEL(skip_4)
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movs r2, r3
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subs r0, r0, #(4 * BLOCK_SIZE)
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LOCAL_LABEL(skip_4):
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# else
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movhs r2, r3
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subhs ip, #(4 * 12)
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subhs ip, #(4 * BLOCK_SIZE)
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# endif
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lsr r3, r2, #2
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lsrs r3, r2, #2
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cmp r3, r1
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# if __ARM_ARCH_ISA_THUMB == 1
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blo LOCAL_LABEL(skip_2)
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movs r2, r3
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subs r0, r0, #(2 * BLOCK_SIZE)
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LOCAL_LABEL(skip_2):
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# else
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movhs r2, r3
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subhs ip, ip, #(2 * 12)
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subhs ip, ip, #(2 * BLOCK_SIZE)
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# endif
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/* Last block, no need to update r2 or r3. */
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cmp r1, r2, lsr #1
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subls ip, ip, #(1 * 12)
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# if __ARM_ARCH_ISA_THUMB == 1
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lsrs r3, r2, #1
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cmp r3, r1
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blo LOCAL_LABEL(skip_1)
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subs r0, r0, #(1 * BLOCK_SIZE)
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LOCAL_LABEL(skip_1):
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movs r2, r0
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mov r0, ip
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movs r3, #0
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JMP (r2)
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mov r3, #0
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# else
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cmp r1, r2, lsr #1
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subls ip, ip, #(1 * BLOCK_SIZE)
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movs r3, #0
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JMP(ip)
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# endif
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# endif
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# endif /* __ARM_FEATURE_CLZ */
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#define IMM #
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/* due to the range limit of branch in Thumb1, we have to place the
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block closer */
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LOCAL_LABEL(divby0):
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movs r0, #0
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# if defined(__ARM_EABI__)
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bl __aeabi_idiv0 // due to relocation limit, can't use b.
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# endif
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JMP(lr)
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#if __ARM_ARCH_ISA_THUMB == 1
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#define block(shift) \
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lsls r2, r1, IMM shift; \
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cmp r0, r2; \
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blo LOCAL_LABEL(block_skip_##shift); \
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subs r0, r0, r2; \
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LOCAL_LABEL(block_skip_##shift) :; \
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adcs r3, r3 /* same as ((r3 << 1) | Carry). Carry is set if r0 >= r2. */
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/* TODO: if current location counter is not not word aligned, we don't
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need the .p2align and nop */
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/* Label div0block must be word-aligned. First align block 31 */
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.p2align 2
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nop /* Padding to align div0block as 31 blocks = 310 bytes */
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#else
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#define block(shift) \
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cmp r0, r1, lsl IMM shift; \
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ITT(hs); \
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WIDE(addhs) r3, r3, IMM (1 << shift); \
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WIDE(subhs) r0, r0, r1, lsl IMM shift
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#endif
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block(31)
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block(30)
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@ -159,14 +252,6 @@ LOCAL_LABEL(div0block):
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JMP(lr)
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#endif /* __ARM_ARCH_EXT_IDIV__ */
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LOCAL_LABEL(divby0):
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mov r0, #0
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#ifdef __ARM_EABI__
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b __aeabi_idiv0
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#else
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JMP(lr)
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#endif
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END_COMPILERRT_FUNCTION(__udivsi3)
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NO_EXEC_STACK_DIRECTIVE
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@ -71,7 +71,8 @@
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#define ARM_HAS_BX
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#endif
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#if !defined(__ARM_FEATURE_CLZ) && \
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(__ARM_ARCH >= 6 || (__ARM_ARCH == 5 && !defined(__ARM_ARCH_5__)))
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((__ARM_ARCH >= 6 && __ARM_ARCH_PROFILE != 'M') || \
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(__ARM_ARCH == 5 && !defined(__ARM_ARCH_5__)))
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#define __ARM_FEATURE_CLZ
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#endif
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