forked from OSchip/llvm-project
[AMDGPU] Spill CSR VGPR which is reserved for SGPR spills
Update logic for reserving VGPR for SGPR spills. A CSR VGPR being reserved for SGPR spills could be clobbered if there were no free lower VGPR's available. Create a stack object so that it will be spilled in the prologue. Also adds more tests. Differential Revision: https://reviews.llvm.org/D83730
This commit is contained in:
Austin Kerbow
parent
834133c950
commit
adeeac9d5a
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@ -233,10 +233,18 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
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// Find lowest available VGPR and use it as VGPR reserved for SGPR spills.
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static bool lowerShiftReservedVGPR(MachineFunction &MF,
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const GCNSubtarget &ST) {
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SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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const Register PreReservedVGPR = FuncInfo->VGPRReservedForSGPRSpill;
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// Early out if pre-reservation of a VGPR for SGPR spilling is disabled.
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if (!PreReservedVGPR)
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return false;
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// If there are no free lower VGPRs available, default to using the
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// pre-reserved register instead.
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Register LowestAvailableVGPR = PreReservedVGPR;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
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Register LowestAvailableVGPR, ReservedVGPR;
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ArrayRef<MCPhysReg> AllVGPR32s = ST.getRegisterInfo()->getAllVGPR32(MF);
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for (MCPhysReg Reg : AllVGPR32s) {
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if (MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg)) {
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@ -245,26 +253,29 @@ static bool lowerShiftReservedVGPR(MachineFunction &MF,
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}
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}
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if (!LowestAvailableVGPR)
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return false;
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ReservedVGPR = FuncInfo->VGPRReservedForSGPRSpill;
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const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
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int i = 0;
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Optional<int> FI;
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// Check if we are reserving a CSR. Create a stack object for a possible spill
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// in the function prologue.
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if (FuncInfo->isCalleeSavedReg(CSRegs, LowestAvailableVGPR))
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FI = FrameInfo.CreateSpillStackObject(4, Align(4));
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// Find saved info about the pre-reserved register.
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const auto *ReservedVGPRInfoItr =
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std::find_if(FuncInfo->getSGPRSpillVGPRs().begin(),
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FuncInfo->getSGPRSpillVGPRs().end(),
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[PreReservedVGPR](const auto &SpillRegInfo) {
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return SpillRegInfo.VGPR == PreReservedVGPR;
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});
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assert(ReservedVGPRInfoItr != FuncInfo->getSGPRSpillVGPRs().end());
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auto Index =
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std::distance(FuncInfo->getSGPRSpillVGPRs().begin(), ReservedVGPRInfoItr);
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FuncInfo->setSGPRSpillVGPRs(LowestAvailableVGPR, FI, Index);
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for (MachineBasicBlock &MBB : MF) {
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for (auto Reg : FuncInfo->getSGPRSpillVGPRs()) {
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if (Reg.VGPR == ReservedVGPR) {
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MBB.removeLiveIn(ReservedVGPR);
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MBB.addLiveIn(LowestAvailableVGPR);
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Optional<int> FI;
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if (FuncInfo->isCalleeSavedReg(CSRegs, LowestAvailableVGPR))
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FI = FrameInfo.CreateSpillStackObject(4, Align(4));
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FuncInfo->setSGPRSpillVGPRs(LowestAvailableVGPR, FI, i);
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}
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++i;
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}
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MBB.addLiveIn(LowestAvailableVGPR);
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MBB.sortUniqueLiveIns();
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}
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@ -5,17 +5,21 @@ define void @child_function() #0 {
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ret void
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}
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; GCN-LABEL: {{^}}parent_func:
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; CHECK: v_writelane_b32 v255, s33, 2
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; CHECK: v_writelane_b32 v255, s30, 0
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; CHECK: v_writelane_b32 v255, s31, 1
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; CHECK: s_swappc_b64 s[30:31], s[4:5]
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; CHECK: v_readlane_b32 s4, v255, 0
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; CHECK: v_readlane_b32 s5, v255, 1
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; CHECK: v_readlane_b32 s33, v255, 2
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; GCN-LABEL: {{^}}reserve_vgpr_with_no_lower_vgpr_available:
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; GCN: buffer_store_dword v255, off, s[0:3], s32
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; GCN: v_writelane_b32 v255, s33, 2
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; GCN: v_writelane_b32 v255, s30, 0
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; GCN: v_writelane_b32 v255, s31, 1
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; GCN: s_swappc_b64 s[30:31], s[4:5]
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; GCN: v_readlane_b32 s4, v255, 0
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; GCN: v_readlane_b32 s5, v255, 1
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; GCN: v_readlane_b32 s33, v255, 2
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; GCN: ; NumVgprs: 256
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define void @parent_func() #0 {
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define void @reserve_vgpr_with_no_lower_vgpr_available() #0 {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %alloca
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call void asm sideeffect "",
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"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
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,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
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@ -47,4 +51,140 @@ define void @parent_func() #0 {
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ret void
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}
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; GCN-LABEL: {{^}}reserve_lowest_available_vgpr:
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; GCN: buffer_store_dword v254, off, s[0:3], s32
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; GCN: v_writelane_b32 v254, s33, 2
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; GCN: v_writelane_b32 v254, s30, 0
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; GCN: v_writelane_b32 v254, s31, 1
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; GCN: s_swappc_b64 s[30:31], s[4:5]
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; GCN: v_readlane_b32 s4, v254, 0
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; GCN: v_readlane_b32 s5, v254, 1
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; GCN: v_readlane_b32 s33, v254, 2
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define void @reserve_lowest_available_vgpr() #0 {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %alloca
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call void asm sideeffect "",
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"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
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,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
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,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}
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,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39}
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,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49}
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,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
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,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69}
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,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79}
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,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89}
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,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
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,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
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,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
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,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
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,~{v130},~{v131},~{v132},~{v133},~{v134},~{v135},~{v136},~{v137},~{v138},~{v139}
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,~{v140},~{v141},~{v142},~{v143},~{v144},~{v145},~{v146},~{v147},~{v148},~{v149}
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,~{v150},~{v151},~{v152},~{v153},~{v154},~{v155},~{v156},~{v157},~{v158},~{v159}
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,~{v160},~{v161},~{v162},~{v163},~{v164},~{v165},~{v166},~{v167},~{v168},~{v169}
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,~{v170},~{v171},~{v172},~{v173},~{v174},~{v175},~{v176},~{v177},~{v178},~{v179}
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,~{v180},~{v181},~{v182},~{v183},~{v184},~{v185},~{v186},~{v187},~{v188},~{v189}
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,~{v190},~{v191},~{v192},~{v193},~{v194},~{v195},~{v196},~{v197},~{v198},~{v199}
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,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
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,~{v210},~{v211},~{v212},~{v213},~{v214},~{v215},~{v216},~{v217},~{v218},~{v219}
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,~{v220},~{v221},~{v222},~{v223},~{v224},~{v225},~{v226},~{v227},~{v228},~{v229}
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,~{v230},~{v231},~{v232},~{v233},~{v234},~{v235},~{v236},~{v237},~{v238},~{v239}
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,~{v240},~{v241},~{v242},~{v243},~{v244},~{v245},~{v246},~{v247},~{v248},~{v249}
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,~{v250},~{v251},~{v252},~{v253}" () #0
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call void @child_function()
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ret void
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}
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; GCN-LABEL: {{^}}reserve_vgpr_with_sgpr_spills:
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; GCN-NOT: buffer_store_dword v255, off, s[0:3], s32
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; GCN: ; def s4
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; GCN: v_writelane_b32 v254, s4, 2
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; GCN: v_readlane_b32 s4, v254, 2
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; GCN: ; use s4
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define void @reserve_vgpr_with_sgpr_spills() #0 {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %alloca
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call void asm sideeffect "",
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"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
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,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
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,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}
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,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39}
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,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49}
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,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
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,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69}
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,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79}
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,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89}
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,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
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,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
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,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
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,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
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,~{v130},~{v131},~{v132},~{v133},~{v134},~{v135},~{v136},~{v137},~{v138},~{v139}
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,~{v140},~{v141},~{v142},~{v143},~{v144},~{v145},~{v146},~{v147},~{v148},~{v149}
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,~{v150},~{v151},~{v152},~{v153},~{v154},~{v155},~{v156},~{v157},~{v158},~{v159}
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,~{v160},~{v161},~{v162},~{v163},~{v164},~{v165},~{v166},~{v167},~{v168},~{v169}
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,~{v170},~{v171},~{v172},~{v173},~{v174},~{v175},~{v176},~{v177},~{v178},~{v179}
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,~{v180},~{v181},~{v182},~{v183},~{v184},~{v185},~{v186},~{v187},~{v188},~{v189}
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,~{v190},~{v191},~{v192},~{v193},~{v194},~{v195},~{v196},~{v197},~{v198},~{v199}
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,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
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,~{v210},~{v211},~{v212},~{v213},~{v214},~{v215},~{v216},~{v217},~{v218},~{v219}
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,~{v220},~{v221},~{v222},~{v223},~{v224},~{v225},~{v226},~{v227},~{v228},~{v229}
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,~{v230},~{v231},~{v232},~{v233},~{v234},~{v235},~{v236},~{v237},~{v238},~{v239}
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,~{v240},~{v241},~{v242},~{v243},~{v244},~{v245},~{v246},~{v247},~{v248},~{v249}
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,~{v250},~{v251},~{v252},~{v253}" () #0
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%sgpr = call i32 asm sideeffect "; def $0", "=s" () #0
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%cmp = icmp eq i32 undef, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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call void asm sideeffect "; use $0", "s"(i32 %sgpr) #0
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br label %ret
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ret:
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ret void
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}
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; GCN-LABEL: {{^}}reserve_vgpr_with_tail_call
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; GCN-NOT: buffer_store_dword v255, off, s[0:3], s32
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; GCN-NOT: v_writelane
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; GCN: s_setpc_b64 s[4:5]
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define void @reserve_vgpr_with_tail_call() #0 {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %alloca
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call void asm sideeffect "",
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"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
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,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
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,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}
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,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38},~{v39}
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,~{v40},~{v41},~{v42},~{v43},~{v44},~{v45},~{v46},~{v47},~{v48},~{v49}
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,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
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,~{v60},~{v61},~{v62},~{v63},~{v64},~{v65},~{v66},~{v67},~{v68},~{v69}
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,~{v70},~{v71},~{v72},~{v73},~{v74},~{v75},~{v76},~{v77},~{v78},~{v79}
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,~{v80},~{v81},~{v82},~{v83},~{v84},~{v85},~{v86},~{v87},~{v88},~{v89}
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,~{v90},~{v91},~{v92},~{v93},~{v94},~{v95},~{v96},~{v97},~{v98},~{v99}
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,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
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,~{v110},~{v111},~{v112},~{v113},~{v114},~{v115},~{v116},~{v117},~{v118},~{v119}
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,~{v120},~{v121},~{v122},~{v123},~{v124},~{v125},~{v126},~{v127},~{v128},~{v129}
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,~{v130},~{v131},~{v132},~{v133},~{v134},~{v135},~{v136},~{v137},~{v138},~{v139}
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,~{v140},~{v141},~{v142},~{v143},~{v144},~{v145},~{v146},~{v147},~{v148},~{v149}
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,~{v150},~{v151},~{v152},~{v153},~{v154},~{v155},~{v156},~{v157},~{v158},~{v159}
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,~{v160},~{v161},~{v162},~{v163},~{v164},~{v165},~{v166},~{v167},~{v168},~{v169}
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,~{v170},~{v171},~{v172},~{v173},~{v174},~{v175},~{v176},~{v177},~{v178},~{v179}
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,~{v180},~{v181},~{v182},~{v183},~{v184},~{v185},~{v186},~{v187},~{v188},~{v189}
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,~{v190},~{v191},~{v192},~{v193},~{v194},~{v195},~{v196},~{v197},~{v198},~{v199}
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,~{v200},~{v201},~{v202},~{v203},~{v204},~{v205},~{v206},~{v207},~{v208},~{v209}
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,~{v210},~{v211},~{v212},~{v213},~{v214},~{v215},~{v216},~{v217},~{v218},~{v219}
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,~{v220},~{v221},~{v222},~{v223},~{v224},~{v225},~{v226},~{v227},~{v228},~{v229}
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,~{v230},~{v231},~{v232},~{v233},~{v234},~{v235},~{v236},~{v237},~{v238},~{v239}
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,~{v240},~{v241},~{v242},~{v243},~{v244},~{v245},~{v246},~{v247},~{v248},~{v249}
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,~{v250},~{v251},~{v252},~{v253},~{v254}" () #0
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musttail call void @child_function()
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ret void
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}
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attributes #0 = { nounwind noinline norecurse "amdgpu-flat-work-group-size"="1,256" }
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