forked from OSchip/llvm-project
[AArch64][GlobalISel] Make <8 x s16> for G_INSERT_VECTOR_ELT legal.
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Amara Emerson
parent
6f10998ad8
commit
ade6fa46f9
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@ -597,11 +597,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.minScalarOrElt(0, s8); // Worst case, we need at least s8.
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getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
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.legalIf([=](const LegalityQuery &Query) {
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const LLT &VecTy = Query.Types[0];
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// TODO: Support s8 and s16
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return VecTy == v2s32 || VecTy == v4s32 || VecTy == v2s64;
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});
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.legalIf(typeInSet(0, {v8s16, v2s32, v4s32, v2s64}));
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getActionDefinitionsBuilder(G_BUILD_VECTOR)
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.legalFor({{v8s8, s8},
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@ -0,0 +1,79 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
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---
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name: v8s16
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16
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; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: %val:_(s16) = G_CONSTANT i16 42
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; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
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; CHECK: $q0 = COPY [[IVEC]](<8 x s16>)
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; CHECK: RET_ReallyLR
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%0:_(<8 x s16>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 1
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%val:_(s16) = G_CONSTANT i16 42
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%2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s32)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR
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...
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---
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name: v2s32
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: %val:_(s32) = G_CONSTANT i32 42
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; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
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; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
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; CHECK: RET_ReallyLR
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%0:_(<2 x s32>) = COPY $d0
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%1:_(s32) = G_CONSTANT i32 1
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%val:_(s32) = G_CONSTANT i32 42
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%2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR
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...
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---
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name: v4s32
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v4s32
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: %val:_(s32) = G_CONSTANT i32 42
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; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
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; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
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; CHECK: RET_ReallyLR
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%0:_(<4 x s32>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 1
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%val:_(s32) = G_CONSTANT i32 42
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%2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s32)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR
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...
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---
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name: v2s64
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v2s64
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: %val:_(s64) = G_CONSTANT i64 42
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; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32)
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; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
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; CHECK: RET_ReallyLR
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%0:_(<2 x s64>) = COPY $q0
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%1:_(s32) = G_CONSTANT i32 1
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%val:_(s64) = G_CONSTANT i64 42
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%2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s32)
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR
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...
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@ -1,6 +1,33 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
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---
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name: v8s16_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q1, $h0
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; CHECK-LABEL: name: v8s16_fpr
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; CHECK: liveins: $q1, $h0
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
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; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY [[INSvi16lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(s16) = COPY $h0
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%1:fpr(<8 x s16>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v4s32_fpr
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alignment: 4
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legalized: true
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