forked from OSchip/llvm-project
* add some assertions for sanity checking.
* remove some old code that was needed when we'd put ESP in the scale instead of the base of some instructions. * Fix a bug with the P modifier in inline asm that caused us to drop it. llvm-svn: 75077
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@ -490,6 +490,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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} else {
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FnStubs.insert(Name);
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printSuffixedName(Name, "$stub");
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assert(MO.getTargetFlags() == 0);
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}
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} else if (GV->hasHiddenVisibility()) {
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if (!GV->isDeclaration() && !GV->hasCommonLinkage())
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@ -498,10 +499,12 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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else {
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HiddenGVStubs.insert(Name);
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printSuffixedName(Name, "$non_lazy_ptr");
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assert(MO.getTargetFlags() == 0);
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}
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} else {
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GVStubs.insert(Name);
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printSuffixedName(Name, "$non_lazy_ptr");
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assert(MO.getTargetFlags() == 0);
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}
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} else {
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O << Name;
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@ -512,8 +515,10 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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PrintPICBaseSymbol();
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}
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} else {
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if (GV->hasDLLImportLinkage())
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if (GV->hasDLLImportLinkage()) {
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O << "__imp_";
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assert(MO.getTargetFlags() == 0);
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}
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O << Name;
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}
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@ -581,8 +586,8 @@ void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
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void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
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const char *Modifier) {
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MachineOperand BaseReg = MI->getOperand(Op);
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MachineOperand IndexReg = MI->getOperand(Op+2);
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const MachineOperand &BaseReg = MI->getOperand(Op);
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const MachineOperand &IndexReg = MI->getOperand(Op+2);
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const MachineOperand &DispSpec = MI->getOperand(Op+3);
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if (DispSpec.isGlobal() ||
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@ -596,27 +601,24 @@ void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
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O << DispVal;
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}
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if ((IndexReg.getReg() || BaseReg.getReg()) &&
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(Modifier == 0 || strcmp(Modifier, "no-rip"))) {
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unsigned ScaleVal = MI->getOperand(Op+1).getImm();
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unsigned BaseRegOperand = 0, IndexRegOperand = 2;
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// There are cases where we can end up with ESP/RSP in the indexreg slot.
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// If this happens, swap the base/index register to support assemblers that
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// don't work when the index is *SP.
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if (IndexReg.getReg() == X86::ESP || IndexReg.getReg() == X86::RSP) {
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assert(ScaleVal == 1 && "Scale not supported for stack pointer!");
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std::swap(BaseReg, IndexReg);
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std::swap(BaseRegOperand, IndexRegOperand);
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}
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// If we really don't want to print out (rip), don't.
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bool HasBaseReg = BaseReg.getReg() != 0;
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if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
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BaseReg.getReg() == X86::RIP)
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HasBaseReg = false;
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if (IndexReg.getReg() || HasBaseReg) {
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assert(IndexReg.getReg() != X86::ESP &&
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"X86 doesn't allow scaling by ESP");
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O << '(';
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if (BaseReg.getReg())
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printOperand(MI, Op+BaseRegOperand, Modifier);
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if (HasBaseReg)
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printOperand(MI, Op, Modifier);
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if (IndexReg.getReg()) {
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O << ',';
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printOperand(MI, Op+IndexRegOperand, Modifier);
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printOperand(MI, Op+2, Modifier);
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unsigned ScaleVal = MI->getOperand(Op+1).getImm();
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if (ScaleVal != 1)
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O << ',' << ScaleVal;
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}
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@ -627,11 +629,11 @@ void X86ATTAsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
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void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
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const char *Modifier) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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MachineOperand Segment = MI->getOperand(Op+4);
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const MachineOperand &Segment = MI->getOperand(Op+4);
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if (Segment.getReg()) {
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printOperand(MI, Op+4, Modifier);
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O << ':';
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}
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printOperand(MI, Op+4, Modifier);
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O << ':';
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}
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printLeaMemReference(MI, Op, Modifier);
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}
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@ -28,7 +28,7 @@ entry:
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; CHECK-64: movl %gs:per_cpu__cpu_number,%eax
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; CHECK-32: test2:
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; FIXME broken: movl %gs:(%eax),%eax
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; CHECK-32: movl %gs:(%eax),%eax
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%A = call i32 asm "movl %gs:${1:P},$0",
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"=r,*m"(i32* @per_cpu__cpu_number) nounwind
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