forked from OSchip/llvm-project
[X86][SSE] Merge combineExtractVectorElt_SSE into combineExtractVectorElt. NFCI.
We still early-out for X86ISD::PEXTRW/X86ISD::PEXTRB so no actual change in behaviour, but it'll make it easier to add support in a future patch. llvm-svn: 317485
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@ -30488,6 +30488,13 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
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if (SDValue NewOp = combineExtractWithShuffle(N, DAG, DCI, Subtarget))
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return NewOp;
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// TODO - Remove this once we can handle the implicit zero-extension of
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// X86ISD::PEXTRW/X86ISD::PEXTRB in:
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// XFormVExtractWithShuffleIntoLoad, combineHorizontalPredicateResult and
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// combineBasicSADPattern.
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if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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return SDValue();
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if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
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return NewOp;
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@ -30635,16 +30642,6 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// TODO - merge with combineExtractVectorElt once it can handle the implicit
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// zero-extension of X86ISD::PINSRW/X86ISD::PINSRB in:
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// XFormVExtractWithShuffleIntoLoad, combineHorizontalPredicateResult and
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// combineBasicSADPattern.
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static SDValue combineExtractVectorElt_SSE(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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return combineExtractWithShuffle(N, DAG, DCI, Subtarget);
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}
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/// If a vector select has an operand that is -1 or 0, try to simplify the
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/// select to a bitwise logic operation.
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/// TODO: Move to DAGCombiner, possibly using TargetLowering::hasAndNot()?
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@ -36767,10 +36764,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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switch (N->getOpcode()) {
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default: break;
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case ISD::EXTRACT_VECTOR_ELT:
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return combineExtractVectorElt(N, DAG, DCI, Subtarget);
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case X86ISD::PEXTRW:
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case X86ISD::PEXTRB:
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return combineExtractVectorElt_SSE(N, DAG, DCI, Subtarget);
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return combineExtractVectorElt(N, DAG, DCI, Subtarget);
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case ISD::INSERT_SUBVECTOR:
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return combineInsertSubvector(N, DAG, DCI, Subtarget);
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case ISD::EXTRACT_SUBVECTOR:
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