[DAGCombiner][RISCV] Adjust (aext (and (trunc x), cst)) -> (and x, cst) to sext cst based on target preference

RISCV strong prefers i32 values be sign extended to i64. This combine
was always zero extending the constant using APInt methods.

This adjusts the code so that it calls getNode using ISD::ANY_EXTEND instead.
getNode will call TLI.isSExtCheaperThanZExt to decide how to handle
the constant.

Tests were copied from D121598 where I noticed that we were creating
constants that were hard to materialize.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D121650

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -12276,11 +12276,10 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
       !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
                           N0.getValueType())) {
     SDLoc DL(N);
-    SDValue X = N0.getOperand(0).getOperand(0);
-    X = DAG.getAnyExtOrTrunc(X, DL, VT);
-    APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
-    return DAG.getNode(ISD::AND, DL, VT,
-                       X, DAG.getConstant(Mask, DL, VT));
+    SDValue X = DAG.getAnyExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT);
+    SDValue Y = DAG.getNode(ISD::ANY_EXTEND, DL, VT, N0.getOperand(1));
+    assert(isa<ConstantSDNode>(Y) && "Expected constant to be folded!");
+    return DAG.getNode(ISD::AND, DL, VT, X, Y);
   }
 
   // fold (aext (load x)) -> (aext (truncate (extload x)))

llvm/test/CodeGen/RISCV/and.ll

@@ -70,3 +70,32 @@ define i64 @and64_0xfff(i64 %x) {
   ret i64 %a
 }
 
+define i32 @and32_0xfffff000(i32 %x) {
+; RV32I-LABEL: and32_0xfffff000:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1048575
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and32_0xfffff000:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1048575
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = and i32 %x, -4096
+  ret i32 %a
+}
+
+define i32 @and32_0xfffffa00(i32 %x) {
+; RV32I-LABEL: and32_0xfffffa00:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, -1536
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and32_0xfffffa00:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, -1536
+; RV64I-NEXT:    ret
+  %a = and i32 %x, -1536
+  ret i32 %a
+}