forked from OSchip/llvm-project
[X86] Change signature of EmitNops. NFC.
This is to support https://reviews.llvm.org/D81301.
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@ -96,8 +96,8 @@ struct NoAutoPaddingScope {
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};
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// Emit a minimal sequence of nops spanning NumBytes bytes.
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static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
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const MCSubtargetInfo &STI);
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static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
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const X86Subtarget *Subtarget);
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void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
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const MCSubtargetInfo &STI,
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@ -117,8 +117,8 @@ void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
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MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
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if (InShadow && CurrentShadowSize < RequiredShadowSize) {
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InShadow = false;
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EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
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MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
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emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
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&MF->getSubtarget<X86Subtarget>());
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}
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}
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@ -1082,29 +1082,29 @@ void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
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/// Return the longest nop which can be efficiently decoded for the given
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/// target cpu. 15-bytes is the longest single NOP instruction, but some
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/// platforms can't decode the longest forms efficiently.
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static unsigned MaxLongNopLength(const MCSubtargetInfo &STI) {
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static unsigned maxLongNopLength(const X86Subtarget *Subtarget) {
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uint64_t MaxNopLength = 10;
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if (STI.getFeatureBits()[X86::ProcIntelSLM])
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if (Subtarget->getFeatureBits()[X86::ProcIntelSLM])
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MaxNopLength = 7;
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else if (STI.getFeatureBits()[X86::FeatureFast15ByteNOP])
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else if (Subtarget->getFeatureBits()[X86::FeatureFast15ByteNOP])
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MaxNopLength = 15;
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else if (STI.getFeatureBits()[X86::FeatureFast11ByteNOP])
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else if (Subtarget->getFeatureBits()[X86::FeatureFast11ByteNOP])
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MaxNopLength = 11;
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return MaxNopLength;
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}
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/// Emit the largest nop instruction smaller than or equal to \p NumBytes
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/// bytes. Return the size of nop emitted.
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static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
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const MCSubtargetInfo &STI) {
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if (!Is64Bit) {
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static unsigned emitNop(MCStreamer &OS, unsigned NumBytes,
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const X86Subtarget *Subtarget) {
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if (!Subtarget->is64Bit()) {
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// TODO Do additional checking if the CPU supports multi-byte nops.
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OS.emitInstruction(MCInstBuilder(X86::NOOP), STI);
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OS.emitInstruction(MCInstBuilder(X86::NOOP), *Subtarget);
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return 1;
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}
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// Cap a single nop emission at the profitable value for the target
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NumBytes = std::min(NumBytes, MaxLongNopLength(STI));
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NumBytes = std::min(NumBytes, maxLongNopLength(Subtarget));
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unsigned NopSize;
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unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
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@ -1178,10 +1178,11 @@ static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
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switch (Opc) {
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default: llvm_unreachable("Unexpected opcode");
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case X86::NOOP:
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OS.emitInstruction(MCInstBuilder(Opc), STI);
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OS.emitInstruction(MCInstBuilder(Opc), *Subtarget);
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break;
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case X86::XCHG16ar:
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OS.emitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI);
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OS.emitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX),
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*Subtarget);
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break;
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case X86::NOOPL:
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case X86::NOOPW:
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@ -1191,7 +1192,7 @@ static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
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.addReg(IndexReg)
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.addImm(Displacement)
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.addReg(SegmentReg),
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STI);
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*Subtarget);
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break;
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}
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assert(NopSize <= NumBytes && "We overemitted?");
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@ -1199,12 +1200,12 @@ static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
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}
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/// Emit the optimal amount of multi-byte nops on X86.
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static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
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const MCSubtargetInfo &STI) {
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static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
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const X86Subtarget *Subtarget) {
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unsigned NopsToEmit = NumBytes;
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(void)NopsToEmit;
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while (NumBytes) {
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NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
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NumBytes -= emitNop(OS, NumBytes, Subtarget);
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assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
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}
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}
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@ -1217,8 +1218,7 @@ void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
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StatepointOpers SOpers(&MI);
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if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
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EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
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getSubtargetInfo());
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emitX86Nops(*OutStreamer, PatchBytes, Subtarget);
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} else {
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// Lower call target and choose correct opcode
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const MachineOperand &CallTarget = SOpers.getCallTarget();
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@ -1350,8 +1350,7 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
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// bytes too, so the check on MinSize is important.
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MCI.setOpcode(X86::PUSH64rmr);
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} else {
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unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
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getSubtargetInfo());
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unsigned NopSize = emitNop(*OutStreamer, MinSize, Subtarget);
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assert(NopSize == MinSize && "Could not implement MinSize!");
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(void)NopSize;
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}
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@ -1435,8 +1434,7 @@ void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
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assert(NumBytes >= EncodedBytes &&
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"Patchpoint can't request size less than the length of a call.");
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EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
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getSubtargetInfo());
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emitX86Nops(*OutStreamer, NumBytes - EncodedBytes, Subtarget);
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}
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void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
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@ -1496,7 +1494,7 @@ void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
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EmitAndCountInstruction(
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MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
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} else {
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EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, 4, Subtarget);
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}
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}
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@ -1525,7 +1523,7 @@ void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
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if (UsedMask[I])
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EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
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else
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EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, 1, Subtarget);
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OutStreamer->AddComment("xray custom event end.");
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@ -1594,7 +1592,7 @@ void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
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EmitAndCountInstruction(
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MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
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} else {
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EmitNops(*OutStreamer, 4, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, 4, Subtarget);
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}
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}
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@ -1628,7 +1626,7 @@ void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
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if (UsedMask[I])
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EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
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else
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EmitNops(*OutStreamer, 1, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, 1, Subtarget);
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OutStreamer->AddComment("xray typed event end.");
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@ -1648,7 +1646,7 @@ void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
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.getValueAsString()
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.getAsInteger(10, Num))
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return;
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EmitNops(*OutStreamer, Num, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, Num, Subtarget);
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return;
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}
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// We want to emit the following pattern:
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@ -1672,7 +1670,7 @@ void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
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// an operand (computed as an offset from the jmp instruction).
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// FIXME: Find another less hacky way do force the relative jump.
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OutStreamer->emitBytes("\xeb\x09");
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EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, 9, Subtarget);
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recordSled(CurSled, MI, SledKind::FUNCTION_ENTER, 2);
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}
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@ -1704,7 +1702,7 @@ void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
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if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
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Ret.addOperand(MaybeOperand.getValue());
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OutStreamer->emitInstruction(Ret, getSubtargetInfo());
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EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, 10, Subtarget);
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recordSled(CurSled, MI, SledKind::FUNCTION_EXIT, 2);
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}
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@ -1727,7 +1725,7 @@ void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
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// an operand (computed as an offset from the jmp instruction).
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// FIXME: Find another less hacky way do force the relative jump.
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OutStreamer->emitBytes("\xeb\x09");
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EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
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emitX86Nops(*OutStreamer, 9, Subtarget);
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OutStreamer->emitLabel(Target);
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recordSled(CurSled, MI, SledKind::TAIL_CALL, 2);
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