forked from OSchip/llvm-project
[AArch64] NFC: Generalize emitFrameOffset to support more than byte offsets.
Refactor emitFrameOffset to accept a StackOffset struct as its offset argument. This method currently only supports byte offsets (MVT::i8) but will be extended in a later patch to support scalable offsets (MVT::nxv1i8) as well. Reviewers: thegameg, rovka, t.p.northover, efriedma, greened Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D61436 llvm-svn: 368049
This commit is contained in:
Sander de Smalen
parent
fc34a536d0
commit
ad7e95df5a
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@ -2972,23 +2972,29 @@ void AArch64InstrInfo::loadRegFromStackSlot(
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MI.addMemOperand(MMO);
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}
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void llvm::emitFrameOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
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unsigned DestReg, unsigned SrcReg,
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StackOffset SOffset, const TargetInstrInfo *TII,
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MachineInstr::MIFlag Flag, bool SetNZCV,
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bool NeedsWinCFI, bool *HasWinCFI) {
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int64_t Offset;
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SOffset.getForFrameOffset(Offset);
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if (DestReg == SrcReg && Offset == 0)
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return;
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assert((DestReg != AArch64::SP || Offset % 16 == 0) &&
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"SP increment/decrement not 16-byte aligned");
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bool isSub = Offset < 0;
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if (isSub)
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Offset = -Offset;
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// Helper function to emit a frame offset adjustment from a given
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// pointer (SrcReg), stored into DestReg. This function is explicit
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// in that it requires the opcode.
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static void emitFrameOffsetAdj(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DestReg,
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unsigned SrcReg, int64_t Offset, unsigned Opc,
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const TargetInstrInfo *TII,
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MachineInstr::MIFlag Flag, bool NeedsWinCFI,
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bool *HasWinCFI) {
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int Sign = 1;
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unsigned MaxEncoding, ShiftSize;
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switch (Opc) {
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case AArch64::ADDXri:
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case AArch64::ADDSXri:
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case AArch64::SUBXri:
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case AArch64::SUBSXri:
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MaxEncoding = 0xfff;
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ShiftSize = 12;
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break;
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default:
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llvm_unreachable("Unsupported opcode");
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}
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// FIXME: If the offset won't fit in 24-bits, compute the offset into a
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// scratch register. If DestReg is a virtual register, use it as the
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@ -3001,65 +3007,77 @@ void llvm::emitFrameOffset(MachineBasicBlock &MBB,
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// of code.
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// assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
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unsigned Opc;
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if (SetNZCV)
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Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri;
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else
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Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri;
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const unsigned MaxEncoding = 0xfff;
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const unsigned ShiftSize = 12;
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const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
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while (((unsigned)Offset) >= (1 << ShiftSize)) {
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unsigned ThisVal;
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if (((unsigned)Offset) > MaxEncodableValue) {
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ThisVal = MaxEncodableValue;
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} else {
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ThisVal = Offset & MaxEncodableValue;
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do {
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unsigned ThisVal = std::min<unsigned>(Offset, MaxEncodableValue);
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unsigned LocalShiftSize = 0;
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if (ThisVal > MaxEncoding) {
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ThisVal = ThisVal >> ShiftSize;
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LocalShiftSize = ShiftSize;
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}
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assert((ThisVal >> ShiftSize) <= MaxEncoding &&
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"Encoding cannot handle value that big");
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BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
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.addReg(SrcReg)
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.addImm(ThisVal >> ShiftSize)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftSize))
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.setMIFlag(Flag);
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auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
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.addReg(SrcReg)
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.addImm(Sign * (int)ThisVal);
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if (ShiftSize)
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MBI = MBI.addImm(
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AArch64_AM::getShifterImm(AArch64_AM::LSL, LocalShiftSize));
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MBI = MBI.setMIFlag(Flag);
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if (NeedsWinCFI && SrcReg == AArch64::SP && DestReg == AArch64::SP) {
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if (NeedsWinCFI) {
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assert(Sign == 1 && "SEH directives should always have a positive sign");
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int Imm = (int)(ThisVal << LocalShiftSize);
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if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) ||
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(SrcReg == AArch64::FP && DestReg == AArch64::SP)) {
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if (HasWinCFI)
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*HasWinCFI = true;
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if (Imm == 0)
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_SetFP)).setMIFlag(Flag);
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else
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_AddFP))
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.addImm(Imm)
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.setMIFlag(Flag);
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assert((Offset - Imm) == 0 && "Expected remaining offset to be zero to "
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"emit a single SEH directive");
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} else if (DestReg == AArch64::SP) {
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if (HasWinCFI)
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*HasWinCFI = true;
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assert(SrcReg == AArch64::SP && "Unexpected SrcReg for SEH_StackAlloc");
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
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.addImm(Imm)
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.setMIFlag(Flag);
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}
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if (HasWinCFI)
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*HasWinCFI = true;
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
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.addImm(ThisVal)
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.setMIFlag(Flag);
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}
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SrcReg = DestReg;
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Offset -= ThisVal;
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if (Offset == 0)
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return;
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}
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BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
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.addReg(SrcReg)
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.addImm(Offset)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
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.setMIFlag(Flag);
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Offset -= ThisVal << LocalShiftSize;
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} while (Offset);
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}
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if (NeedsWinCFI) {
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if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) ||
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(SrcReg == AArch64::FP && DestReg == AArch64::SP)) {
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if (HasWinCFI)
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*HasWinCFI = true;
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if (Offset == 0)
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_SetFP)).
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setMIFlag(Flag);
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else
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_AddFP)).
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addImm(Offset).setMIFlag(Flag);
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} else if (DestReg == AArch64::SP) {
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if (HasWinCFI)
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*HasWinCFI = true;
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc)).
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addImm(Offset).setMIFlag(Flag);
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void llvm::emitFrameOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
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unsigned DestReg, unsigned SrcReg,
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StackOffset Offset, const TargetInstrInfo *TII,
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MachineInstr::MIFlag Flag, bool SetNZCV,
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bool NeedsWinCFI, bool *HasWinCFI) {
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int64_t Bytes;
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Offset.getForFrameOffset(Bytes);
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// First emit non-scalable frame offsets, or a simple 'mov'.
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if (Bytes || (!Offset && SrcReg != DestReg)) {
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assert((DestReg != AArch64::SP || Bytes % 16 == 0) &&
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"SP increment/decrement not 16-byte aligned");
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unsigned Opc = SetNZCV ? AArch64::ADDSXri : AArch64::ADDXri;
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if (Bytes < 0) {
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Bytes = -Bytes;
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Opc = SetNZCV ? AArch64::SUBSXri : AArch64::SUBXri;
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}
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emitFrameOffsetAdj(MBB, MBBI, DL, DestReg, SrcReg, Bytes, Opc, TII, Flag,
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NeedsWinCFI, HasWinCFI);
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SrcReg = DestReg;
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}
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}
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