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Fix the x86-64 side of PR2108 by adding a v2f64 version of 

MOVZQI2PQIrr.  This would be better handled as a dag combine 
(with the goal of eliminating the bitconvert) but I don't know
how to do that safely.  Thoughts welcome.

llvm-svn: 49463
This commit is contained in:
Chris Lattner 2008-04-10 05:13:43 +00:00
parent 57dd77462b
commit ad75302497
2 changed files with 23 additions and 0 deletions
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10
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -2305,6 +2305,16 @@ def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
MOVL_shuffle_mask)))]>;
}
// Handle the v2f64 form of 'MOVZQI2PQIrr' for PR2108. FIXME: this would be
// better written as a dag combine xform.
let AddedComplexity = 15 in
def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
(v2f64 (scalar_to_vector
(f64 (bitconvert GR64:$src)))),
MOVL_shuffle_mask)),
(MOVZQI2PQIrr GR64:$src)>, Requires<[HasSSE3]>;
let AddedComplexity = 20 in {
def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
"movd\t{$src, $dst|$dst, $src}",

13
llvm/test/CodeGen/X86/vec_shuffle-17.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep {movd.*%rdi, %xmm0}
; RUN: llvm-as < %s | llc -march=x86-64 | not grep xor
; PR2108
define <2 x i64> @doload64(i64 %x) nounwind {
entry:
%tmp717 = bitcast i64 %x to double ; <double> [#uses=1]
%tmp8 = insertelement <2 x double> undef, double %tmp717, i32 0 ; <<2 x double>> [#uses=1]
%tmp9 = insertelement <2 x double> %tmp8, double 0.000000e+00, i32 1 ; <<2 x double>> [#uses=1]
%tmp11 = bitcast <2 x double> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp11
}