forked from OSchip/llvm-project
[X86][AVX512] add intrinsics of Scalar FP to integer conversion with rounding mode
Differential Revision: http://reviews.llvm.org/D16629 llvm-svn: 260033
This commit is contained in:
Asaf Badouh
parent
73fc26b44a
commit
ad5c3fc47d
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@ -5098,10 +5098,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Conversion ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_cvtss2usi : GCCBuiltin<"__builtin_ia32_cvtss2usi">,
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Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtss2usi64 : GCCBuiltin<"__builtin_ia32_cvtss2usi64">,
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Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvttss2si : GCCBuiltin<"__builtin_ia32_vcvttss2si32">,
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Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvttss2si64 : GCCBuiltin<"__builtin_ia32_vcvttss2si64">,
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@ -5116,11 +5112,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_cvtusi642ss : GCCBuiltin<"__builtin_ia32_cvtusi2ss64">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
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llvm_i64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsd2usi : GCCBuiltin<"__builtin_ia32_cvtsd2usi">,
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Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsd2usi64 : GCCBuiltin<"__builtin_ia32_cvtsd2usi64">,
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Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_avx512_cvttsd2si : GCCBuiltin<"__builtin_ia32_vcvttsd2si32">,
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Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvttsd2si64 : GCCBuiltin<"__builtin_ia32_vcvttsd2si64">,
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@ -5135,7 +5126,22 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_cvtusi642sd : GCCBuiltin<"__builtin_ia32_cvtusi2sd64">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
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llvm_i64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtss2usi32 : GCCBuiltin<"__builtin_ia32_vcvtss2usi32">,
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Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtss2usi64 : GCCBuiltin<"__builtin_ia32_vcvtss2usi64">,
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Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtss2si32 : GCCBuiltin<"__builtin_ia32_vcvtss2si32">,
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Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtss2si64 : GCCBuiltin<"__builtin_ia32_vcvtss2si64">,
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Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtsd2usi32 : GCCBuiltin<"__builtin_ia32_vcvtsd2usi32">,
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Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtsd2usi64 : GCCBuiltin<"__builtin_ia32_vcvtsd2usi64">,
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Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtsd2si32 : GCCBuiltin<"__builtin_ia32_vcvtsd2si32">,
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Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_vcvtsd2si64 : GCCBuiltin<"__builtin_ia32_vcvtsd2si64">,
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Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsi2ss32 : GCCBuiltin<"__builtin_ia32_cvtsi2ss32">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
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llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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@ -21148,6 +21148,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
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case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
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case X86ISD::MULTISHIFT: return "X86ISD::MULTISHIFT";
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case X86ISD::SCALAR_FP_TO_SINT_RND: return "X86ISD::SCALAR_FP_TO_SINT_RND";
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case X86ISD::SCALAR_FP_TO_UINT_RND: return "X86ISD::SCALAR_FP_TO_UINT_RND";
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}
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return nullptr;
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}
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@ -470,6 +470,8 @@ namespace llvm {
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// Vector float/double to signed/unsigned integer.
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FP_TO_SINT_RND, FP_TO_UINT_RND,
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// Scalar float/double to signed/unsigned integer.
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SCALAR_FP_TO_SINT_RND, SCALAR_FP_TO_UINT_RND,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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@ -4945,54 +4945,66 @@ def : Pat<(f64 (uint_to_fp GR64:$src)),
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//===----------------------------------------------------------------------===//
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// AVX-512 Scalar convert from float/double to integer
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//===----------------------------------------------------------------------===//
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multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
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RegisterClass DstRC, Intrinsic Int,
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Operand memop, ComplexPattern mem_cpat, string asm> {
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multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT ,
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X86VectorVTInfo DstVT, SDNode OpNode, string asm> {
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let hasSideEffects = 0, Predicates = [HasAVX512] in {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
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def rr : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
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def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
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!strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
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[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 FROUND_CURRENT)))]>,
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EVEX, VEX_LIG;
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def rb : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc),
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!strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
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[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))]>,
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EVEX, VEX_LIG, EVEX_B, EVEX_RC;
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let mayLoad = 1 in
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def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
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} // hasSideEffects = 0, Predicates = [HasAVX512]
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def rm : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.ScalarMemOp:$src),
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!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
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[(set DstVT.RC:$dst, (OpNode
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(SrcVT.VT (scalar_to_vector (SrcVT.ScalarLdFrag addr:$src))),
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(i32 FROUND_CURRENT)))]>,
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EVEX, VEX_LIG;
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} // hasSideEffects = 0, Predicates = [HasAVX512]
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}
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// Convert float/double to signed/unsigned int 32/64
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defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
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ssmem, sse_load_f32, "cvtss2si">,
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defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,
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X86cvtss2si, "cvtss2si">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
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int_x86_sse_cvtss2si64,
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ssmem, sse_load_f32, "cvtss2si">,
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defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info,
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X86cvtss2si, "cvtss2si">,
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XS, VEX_W, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
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int_x86_avx512_cvtss2usi,
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ssmem, sse_load_f32, "cvtss2usi">,
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defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info,
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X86cvtss2usi, "cvtss2usi">,
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XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
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int_x86_avx512_cvtss2usi64, ssmem,
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sse_load_f32, "cvtss2usi">, XS, VEX_W,
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defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info,
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X86cvtss2usi, "cvtss2usi">, XS, VEX_W,
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EVEX_CD8<32, CD8VT1>;
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defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
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sdmem, sse_load_f64, "cvtsd2si">,
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defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info,
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X86cvtsd2si, "cvtsd2si">,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
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int_x86_sse2_cvtsd2si64,
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sdmem, sse_load_f64, "cvtsd2si">,
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defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info,
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X86cvtsd2si, "cvtsd2si">,
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XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
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int_x86_avx512_cvtsd2usi,
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sdmem, sse_load_f64, "cvtsd2usi">,
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defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info,
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X86cvtsd2usi, "cvtsd2usi">,
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XD, EVEX_CD8<64, CD8VT1>;
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defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
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int_x86_avx512_cvtsd2usi64, sdmem,
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sse_load_f64, "cvtsd2usi">, XD, VEX_W,
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defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
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X86cvtsd2usi, "cvtsd2usi">, XD, VEX_W,
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EVEX_CD8<64, CD8VT1>;
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// The SSE version of these instructions are disabled for AVX512.
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// Therefore, the SSE intrinsics are mapped to the AVX512 instructions.
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let Predicates = [HasAVX512] in {
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def : Pat<(i32 (int_x86_sse_cvtss2si (v4f32 VR128X:$src))),
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(VCVTSS2SIZrr (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
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def : Pat<(i64 (int_x86_sse_cvtss2si64 (v4f32 VR128X:$src))),
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(VCVTSS2SI64Zrr (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
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def : Pat<(i32 (int_x86_sse2_cvtsd2si (v2f64 VR128X:$src))),
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(VCVTSD2SIZrr (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
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def : Pat<(i64 (int_x86_sse2_cvtsd2si64 (v2f64 VR128X:$src))),
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(VCVTSD2SI64Zrr (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
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} // HasAVX512
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let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
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defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
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int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
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@ -542,6 +542,12 @@ def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>
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def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
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def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
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def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
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def X86cvtsd2si : SDNode<"X86ISD::SCALAR_FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
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def X86cvtsd2usi : SDNode<"X86ISD::SCALAR_FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
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def X86cvtss2si : SDNode<"X86ISD::SCALAR_FP_TO_SINT_RND", SDTSFloatToIntRnd>;
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def X86cvtss2usi : SDNode<"X86ISD::SCALAR_FP_TO_UINT_RND", SDTSFloatToIntRnd>;
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// Vector with rounding mode
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// cvtt fp-to-int staff
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@ -2135,6 +2135,22 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_rsqrt28_ss, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_vcomi_sd, COMI_RM, X86ISD::COMI, X86ISD::UCOMI),
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X86_INTRINSIC_DATA(avx512_vcomi_ss, COMI_RM, X86ISD::COMI, X86ISD::UCOMI),
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X86_INTRINSIC_DATA(avx512_vcvtsd2si32, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_SINT_RND, 0),
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X86_INTRINSIC_DATA(avx512_vcvtsd2si64, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_SINT_RND, 0),
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X86_INTRINSIC_DATA(avx512_vcvtsd2usi32, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_UINT_RND, 0),
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X86_INTRINSIC_DATA(avx512_vcvtsd2usi64, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_UINT_RND, 0),
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X86_INTRINSIC_DATA(avx512_vcvtss2si32, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_SINT_RND, 0),
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X86_INTRINSIC_DATA(avx512_vcvtss2si64, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_SINT_RND, 0),
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X86_INTRINSIC_DATA(avx512_vcvtss2usi32, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_UINT_RND, 0),
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X86_INTRINSIC_DATA(avx512_vcvtss2usi64, INTR_TYPE_2OP,
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X86ISD::SCALAR_FP_TO_UINT_RND, 0),
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X86_INTRINSIC_DATA(fma_vfmadd_pd, INTR_TYPE_3OP, X86ISD::FMADD, 0),
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X86_INTRINSIC_DATA(fma_vfmadd_pd_256, INTR_TYPE_3OP, X86ISD::FMADD, 0),
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X86_INTRINSIC_DATA(fma_vfmadd_ps, INTR_TYPE_3OP, X86ISD::FMADD, 0),
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@ -2275,10 +2275,10 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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case llvm::Intrinsic::bswap:
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handleBswap(I);
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break;
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case llvm::Intrinsic::x86_avx512_cvtsd2usi64:
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case llvm::Intrinsic::x86_avx512_cvtsd2usi:
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case llvm::Intrinsic::x86_avx512_cvtss2usi64:
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case llvm::Intrinsic::x86_avx512_cvtss2usi:
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case llvm::Intrinsic::x86_avx512_vcvtsd2usi64:
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case llvm::Intrinsic::x86_avx512_vcvtsd2usi32:
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case llvm::Intrinsic::x86_avx512_vcvtss2usi64:
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case llvm::Intrinsic::x86_avx512_vcvtss2usi32:
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case llvm::Intrinsic::x86_avx512_cvttss2usi64:
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case llvm::Intrinsic::x86_avx512_cvttss2usi:
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case llvm::Intrinsic::x86_avx512_cvttsd2usi64:
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@ -424,12 +424,154 @@ declare i64 @llvm.x86.avx512.cvttss2usi64(<4 x float>, i32) nounwind readnone
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define i64 @test_x86_avx512_cvtsd2usi64(<2 x double> %a0) {
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; CHECK-LABEL: test_x86_avx512_cvtsd2usi64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsd2usi %xmm0, %rax
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; CHECK-NEXT: vcvtsd2usi %xmm0, %rcx
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; CHECK-NEXT: vcvtsd2usi {rz-sae}, %xmm0, %rax
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; CHECK-NEXT: vcvtsd2usi {rd-sae}, %xmm0, %rdx
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; CHECK-NEXT: addq %rcx, %rax
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; CHECK-NEXT: addq %rdx, %rax
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; CHECK-NEXT: retq
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%res = call i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double> %a0) ; <i64> [#uses=1]
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ret i64 %res
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%res = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> %a0, i32 4)
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%res1 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> %a0, i32 3)
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%res2 = call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> %a0, i32 1)
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%res3 = add i64 %res, %res1
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%res4 = add i64 %res3, %res2
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ret i64 %res4
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}
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declare i64 @llvm.x86.avx512.cvtsd2usi64(<2 x double>) nounwind readnone
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declare i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double>, i32) nounwind readnone
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define i64 @test_x86_avx512_cvtsd2si64(<2 x double> %a0) {
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; CHECK-LABEL: test_x86_avx512_cvtsd2si64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsd2si %xmm0, %rcx
|
||||
; CHECK-NEXT: vcvtsd2si {rz-sae}, %xmm0, %rax
|
||||
; CHECK-NEXT: vcvtsd2si {rd-sae}, %xmm0, %rdx
|
||||
; CHECK-NEXT: addq %rcx, %rax
|
||||
; CHECK-NEXT: addq %rdx, %rax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> %a0, i32 4)
|
||||
%res1 = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> %a0, i32 3)
|
||||
%res2 = call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> %a0, i32 1)
|
||||
%res3 = add i64 %res, %res1
|
||||
%res4 = add i64 %res3, %res2
|
||||
ret i64 %res4
|
||||
}
|
||||
declare i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double>, i32) nounwind readnone
|
||||
|
||||
define i64 @test_x86_avx512_cvtss2usi64(<4 x float> %a0) {
|
||||
; CHECK-LABEL: test_x86_avx512_cvtss2usi64:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtss2usi %xmm0, %rcx
|
||||
; CHECK-NEXT: vcvtss2usi {rz-sae}, %xmm0, %rax
|
||||
; CHECK-NEXT: vcvtss2usi {rd-sae}, %xmm0, %rdx
|
||||
; CHECK-NEXT: addq %rcx, %rax
|
||||
; CHECK-NEXT: addq %rdx, %rax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> %a0, i32 4)
|
||||
%res1 = call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> %a0, i32 3)
|
||||
%res2 = call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> %a0, i32 1)
|
||||
%res3 = add i64 %res, %res1
|
||||
%res4 = add i64 %res3, %res2
|
||||
ret i64 %res4
|
||||
}
|
||||
declare i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float>, i32) nounwind readnone
|
||||
|
||||
define i64 @test_x86_avx512_cvtss2si64(<4 x float> %a0) {
|
||||
; CHECK-LABEL: test_x86_avx512_cvtss2si64:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtss2si %xmm0, %rcx
|
||||
; CHECK-NEXT: vcvtss2si {rz-sae}, %xmm0, %rax
|
||||
; CHECK-NEXT: vcvtss2si {rd-sae}, %xmm0, %rdx
|
||||
; CHECK-NEXT: addq %rcx, %rax
|
||||
; CHECK-NEXT: addq %rdx, %rax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> %a0, i32 4)
|
||||
%res1 = call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> %a0, i32 3)
|
||||
%res2 = call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> %a0, i32 1)
|
||||
%res3 = add i64 %res, %res1
|
||||
%res4 = add i64 %res3, %res2
|
||||
ret i64 %res4
|
||||
}
|
||||
declare i64 @llvm.x86.avx512.vcvtss2si64(<4 x float>, i32) nounwind readnone
|
||||
|
||||
define i32 @test_x86_avx512_cvtsd2usi32(<2 x double> %a0) {
|
||||
; CHECK-LABEL: test_x86_avx512_cvtsd2usi32:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtsd2usi %xmm0, %ecx
|
||||
; CHECK-NEXT: vcvtsd2usi {rz-sae}, %xmm0, %eax
|
||||
; CHECK-NEXT: vcvtsd2usi {rd-sae}, %xmm0, %edx
|
||||
; CHECK-NEXT: addl %ecx, %eax
|
||||
; CHECK-NEXT: addl %edx, %eax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %a0, i32 4)
|
||||
%res1 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %a0, i32 3)
|
||||
%res2 = call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %a0, i32 1)
|
||||
%res3 = add i32 %res, %res1
|
||||
%res4 = add i32 %res3, %res2
|
||||
ret i32 %res4
|
||||
}
|
||||
declare i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double>, i32) nounwind readnone
|
||||
|
||||
define i32 @test_x86_avx512_cvtsd2si32(<2 x double> %a0) {
|
||||
; CHECK-LABEL: test_x86_avx512_cvtsd2si32:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtsd2si %xmm0, %ecx
|
||||
; CHECK-NEXT: vcvtsd2si {rz-sae}, %xmm0, %eax
|
||||
; CHECK-NEXT: vcvtsd2si {rd-sae}, %xmm0, %edx
|
||||
; CHECK-NEXT: addl %ecx, %eax
|
||||
; CHECK-NEXT: addl %edx, %eax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %a0, i32 4)
|
||||
%res1 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %a0, i32 3)
|
||||
%res2 = call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %a0, i32 1)
|
||||
%res3 = add i32 %res, %res1
|
||||
%res4 = add i32 %res3, %res2
|
||||
ret i32 %res4
|
||||
}
|
||||
declare i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double>, i32) nounwind readnone
|
||||
|
||||
define i32 @test_x86_avx512_cvtss2usi32(<4 x float> %a0) {
|
||||
; CHECK-LABEL: test_x86_avx512_cvtss2usi32:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtss2usi %xmm0, %ecx
|
||||
; CHECK-NEXT: vcvtss2usi {rz-sae}, %xmm0, %eax
|
||||
; CHECK-NEXT: vcvtss2usi {rd-sae}, %xmm0, %edx
|
||||
; CHECK-NEXT: addl %ecx, %eax
|
||||
; CHECK-NEXT: addl %edx, %eax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %a0, i32 4)
|
||||
%res1 = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %a0, i32 3)
|
||||
%res2 = call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %a0, i32 1)
|
||||
%res3 = add i32 %res, %res1
|
||||
%res4 = add i32 %res3, %res2
|
||||
ret i32 %res4
|
||||
}
|
||||
declare i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float>, i32) nounwind readnone
|
||||
|
||||
define i32 @test_x86_avx512_cvtss2si32(<4 x float> %a0) {
|
||||
; CHECK-LABEL: test_x86_avx512_cvtss2si32:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: vcvtss2si %xmm0, %ecx
|
||||
; CHECK-NEXT: vcvtss2si {rz-sae}, %xmm0, %eax
|
||||
; CHECK-NEXT: vcvtss2si {rd-sae}, %xmm0, %edx
|
||||
; CHECK-NEXT: addl %ecx, %eax
|
||||
; CHECK-NEXT: addl %edx, %eax
|
||||
; CHECK-NEXT: retq
|
||||
|
||||
%res = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %a0, i32 4)
|
||||
%res1 = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %a0, i32 3)
|
||||
%res2 = call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %a0, i32 1)
|
||||
%res3 = add i32 %res, %res1
|
||||
%res4 = add i32 %res3, %res2
|
||||
ret i32 %res4
|
||||
}
|
||||
declare i32 @llvm.x86.avx512.vcvtss2si32(<4 x float>, i32) nounwind readnone
|
||||
|
||||
define <16 x float> @test_x86_vcvtph2ps_512(<16 x i16> %a0) {
|
||||
; CHECK-LABEL: test_x86_vcvtph2ps_512:
|
||||
|
|
|
|||
Loading…
Reference in New Issue