forked from OSchip/llvm-project
AMDGPU: Don't required structured CFG
The structured CFG is just an aid to inserting exec mask modification instructions, once that is done we don't really need it anymore. We also do not analyze blocks with terminators that modify exec, so this should only be impacting true branches. llvm-svn: 288744
This commit is contained in:
Matt Arsenault
parent
9642b36e91
commit
ad55ee5869
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@ -162,7 +162,6 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
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FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
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TLOF(createTLOF(getTargetTriple())),
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IntrinsicInfo() {
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setRequiresStructuredCFG(true);
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initAsmInfo();
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}
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@ -191,7 +190,9 @@ R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
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TargetOptions Options,
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Optional<Reloc::Model> RM,
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CodeModel::Model CM, CodeGenOpt::Level OL)
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: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
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: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
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setRequiresStructuredCFG(true);
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}
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const R600Subtarget *R600TargetMachine::getSubtargetImpl(
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const Function &F) const {
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@ -8,13 +8,15 @@
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; GCNNOOPT: v_writelane_b32
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; GCN: s_cbranch_scc1 [[END:BB[0-9]+_[0-9]+]]
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; GCN: ; BB#1
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; GCNNOOPT: v_readlane_b32
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; GCNNOOPT: v_readlane_b32
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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; GCNOPT-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; TODO: This waitcnt can be eliminated
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; GCN: {{^}}[[END]]
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define void @test_branch(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %val) #0 {
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%cmp = icmp ne i32 %val, 0
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@ -35,9 +37,10 @@ end:
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; GCN: s_cbranch_vccnz [[END:BB[0-9]+_[0-9]+]]
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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; GCNOPT-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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; TODO: This waitcnt can be eliminated
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; GCN: {{^}}[[END]]
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; GCN: {{^}}[[END]]:
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; GCN: s_endpgm
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define void @test_brcc_i1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i1 %val) #0 {
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%cmp0 = icmp ne i1 %val, 0
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@ -12,9 +12,10 @@
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; GCN: s_cbranch_vccnz
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; GCN: one{{$}}
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; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
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; GCN: buffer_store_short v[[A_F16]]
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; GCN: s_endpgm
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; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
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; SI: s_branch
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; VI: buffer_store_short
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; VI: s_endpgm
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; GCN: two{{$}}
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; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
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@ -47,17 +48,19 @@ two:
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cmp_ngt_f32_e32 vcc, v[[B_F32]], v[[A_F32]]
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; VI: v_cmp_nle_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
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; GCN: s_cbranch_vccnz
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; SI: s_cbranch_vccz
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; VI: s_cbranch_vccnz
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; GCN: one{{$}}
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; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x3800{{$}}
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; GCN: buffer_store_short v[[A_F16]]
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; GCN: s_endpgm
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; VI: one{{$}}
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; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x380{{0|1}}{{$}}
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; GCN: two{{$}}
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; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]]
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; GCN: buffer_store_short v[[B_F16]]
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; GCN: s_endpgm
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; SI: one{{$}}
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; SI: buffer_store_short v[[A_F16]]
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; SI: s_endpgm
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define void @br_cc_f16_imm_a(
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half addrspace(1)* %r,
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half addrspace(1)* %b) {
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@ -87,8 +90,6 @@ two:
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; GCN: one{{$}}
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; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]]
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; GCN: buffer_store_short v[[A_F16]]
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; GCN: s_endpgm
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; GCN: two{{$}}
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; VI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}}
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@ -475,14 +475,13 @@ ret:
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; GCN-LABEL: {{^}}long_branch_hang:
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; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
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; GCN-NEXT: s_cbranch_scc1 [[LONG_BR_0:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: s_branch [[SHORTB:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: s_cbranch_scc0 [[LONG_BR_0:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
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; GCN-NEXT: [[LONG_BR_0]]:
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; GCN: s_add_u32 vcc_lo, vcc_lo, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-(
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; GCN: s_setpc_b64
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; GCN: [[SHORTB]]:
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; GCN-NEXT: [[LONG_BR_0]]:
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; GCN-DAG: v_cmp_lt_i32
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; GCN-DAG: v_cmp_gt_i32
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; GCN: s_cbranch_vccnz
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@ -492,7 +491,6 @@ ret:
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; GCN: [[LONG_BR_DEST0]]
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; GCN: v_cmp_ne_u32_e32
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; GCN-NEXT: ; implicit-def
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; GCN-NEXT: s_cbranch_vccz
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; GCN: s_setpc_b64
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@ -506,11 +506,13 @@ bb:
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bb1:
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%tmp2 = load volatile <4 x float>, <4 x float> addrspace(1)* undef
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%tmp3 = extractelement <4 x float> %tmp2, i32 undef
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call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp2) #0 ; Prevent block optimize out
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br label %bb7
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bb4:
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%tmp5 = load volatile <4 x float>, <4 x float> addrspace(1)* undef
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%tmp6 = extractelement <4 x float> %tmp5, i32 undef
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call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp5) #0 ; Prevent block optimize out
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br label %bb7
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bb7:
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@ -554,11 +556,13 @@ bb:
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bb1: ; preds = %bb
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%tmp2 = load volatile <4 x float>, <4 x float> addrspace(1)* undef
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%tmp3 = insertelement <4 x float> %tmp2, float %val0, i32 undef
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call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp3) #0 ; Prevent block optimize out
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br label %bb7
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bb4: ; preds = %bb
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%tmp5 = load volatile <4 x float>, <4 x float> addrspace(1)* undef
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%tmp6 = insertelement <4 x float> %tmp5, float %val0, i32 undef
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call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp6) #0 ; Prevent block optimize out
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br label %bb7
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bb7: ; preds = %bb4, %bb1
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@ -745,6 +749,8 @@ bb8: ; preds = %bb2
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare void @llvm.amdgcn.s.barrier() #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind convergent }
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@ -1,8 +1,5 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; FIXME: Enabling critical edge splitting will fix this.
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; XFAIL: *
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; Make sure that m0 is not reinitialized in the loop.
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; GCN-LABEL: {{^}}copy_local_to_global_loop_m0_init:
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@ -12,7 +9,9 @@
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; GCN: s_mov_b32 m0, -1
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; GCN: BB0_2:
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; GCN-NOT: m0
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; GCN: ds_read_b32
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; GCN-NOT: m0
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; GCN: buffer_store_dword
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; GCN: s_cbranch_scc0 BB0_2
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@ -1,4 +1,4 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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;
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;
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; Most SALU instructions ignore control flow, so we need to make sure
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@ -9,13 +9,54 @@
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; about instructions in different blocks overwriting each other.
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; SI-LABEL: {{^}}sgpr_if_else_salu_br:
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; SI: s_add
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; SI: s_add
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; SI: s_branch
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; SI: s_sub
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define void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = sub i32 %b, %c
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br label %endif
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else:
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%2 = add i32 %d, %e
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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%4 = add i32 %3, %a
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store i32 %4, i32 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}sgpr_if_else_salu_br_opt:
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; SI: s_cmp_lg_u32
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; SI: s_cbranch_scc0 [[IF:BB[0-9]+_[0-9]+]]
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; SI: ; BB#1: ; %else
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; SI: s_load_dword [[LOAD0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xe
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; SI: s_load_dword [[LOAD1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xf
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; SI-NOT: add
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; SI: s_branch [[ENDIF:BB[0-9]+_[0-9]+]]
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; SI: [[IF]]: ; %if
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; SI: s_load_dword [[LOAD0]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: s_load_dword [[LOAD1]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-NOT: add
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; SI: [[ENDIF]]: ; %endif
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; SI: s_add_i32 s{{[0-9]+}}, [[LOAD0]], [[LOAD1]]
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; SI: buffer_store_dword
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; SI-NEXT: s_endpgm
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define void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = add i32 %b, %c
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br label %endif
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@ -67,7 +108,7 @@ endif:
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; SI: v_cmp_gt_i32_e32 [[CMP_IF:vcc]], 0, [[AVAL]]
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; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]]
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; SI: BB2_2:
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; SI: BB{{[0-9]+}}_2:
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; SI: buffer_load_dword [[AVAL:v[0-9]+]]
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; SI: v_cmp_eq_u32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]]
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; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]]
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; This test checks that no VGPR to SGPR copies are created by the register
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; allocator.
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@ -223,8 +223,15 @@ declare i32 @llvm.SI.packf16(float, float) #1
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; an assertion failure.
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; CHECK-LABEL: {{^}}sample_v3:
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; CHECK: image_sample
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; CHECK: image_sample
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; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11
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; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13
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; CHECK: s_branch
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; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
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; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
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; CHECK: BB{{[0-9]+_[0-9]+}}:
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; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}}
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; CHECK: exp
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; CHECK: s_endpgm
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define amdgpu_ps void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
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@ -241,14 +248,14 @@ entry:
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br i1 %tmp27, label %if, label %else
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if: ; preds = %entry
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%val.if = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> zeroinitializer, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%val.if = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 11, i32 13>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%val.if.0 = extractelement <4 x float> %val.if, i32 0
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%val.if.1 = extractelement <4 x float> %val.if, i32 1
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%val.if.2 = extractelement <4 x float> %val.if, i32 2
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br label %endif
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else: ; preds = %entry
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%val.else = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1, i32 0>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%val.else = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 5, i32 7>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%val.else.0 = extractelement <4 x float> %val.else, i32 0
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%val.else.1 = extractelement <4 x float> %val.else, i32 1
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%val.else.2 = extractelement <4 x float> %val.else, i32 2
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@ -317,9 +324,15 @@ ENDIF69: ; preds = %LOOP68
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; This test checks that image_sample resource descriptors aren't loaded into
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; vgprs. The verifier will fail if this happens.
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; CHECK-LABEL:{{^}}sample_rsrc:
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; CHECK: image_sample
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; CHECK: image_sample
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; CHECK-LABEL:{{^}}sample_rsrc
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; CHECK: s_cmp_eq_u32
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; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]]
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; CHECK: v_add_i32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}
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; [[END]]:
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; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}}
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; CHECK: s_endpgm
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define amdgpu_ps void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
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bb:
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@ -308,10 +308,8 @@ end:
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; CHECK: s_mov_b64 exec, 0
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; CHECK: [[SKIPKILL]]:
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; CHECK: v_cmp_nge_f32
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; CHECK-NEXT: s_cbranch_vccz [[UNREACHABLE:BB[0-9]+_[0-9]+]]
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; CHECK: [[UNREACHABLE]]:
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; CHECK: v_cmp_nge_f32_e32 vcc
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; CHECK-NEXT: BB#3: ; %bb5
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; CHECK-NEXT: .Lfunc_end{{[0-9]+}}
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define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
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bb:
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@ -197,15 +197,15 @@ if.end: ; preds = %if.else, %if.then
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
|
||||
; GCN-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]]
|
||||
|
||||
; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
|
||||
; GCN: buffer_store_dword [[TWO]]
|
||||
; GCN: v_mov_b32_e32 [[IMM_REG:v[0-9]+]], 2
|
||||
; GCN: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]]
|
||||
|
||||
; GCN: [[IF_LABEL]]:
|
||||
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
||||
; GCN: buffer_store_dword [[ONE]]
|
||||
; GCN-NEXT: v_mov_b32_e32 [[IMM_REG]], 1
|
||||
|
||||
; GCN-NEXT: [[ENDIF_LABEL]]:
|
||||
; GCN: buffer_store_dword [[IMM_REG]]
|
||||
|
||||
; GCN: [[ENDIF_LABEL]]:
|
||||
; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3
|
||||
; GCN: buffer_store_dword [[THREE]]
|
||||
; GCN: s_endpgm
|
||||
|
|
|
|||
Loading…
Reference in New Issue