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Determine whether a spill kills the register it's spilling before insertion rather than trying to undo the kill marker afterwards. 

llvm-svn: 46953
This commit is contained in:
Evan Cheng 2008-02-11 08:30:52 +00:00
parent 887f5ebfa9
commit ad4d57a2f5
2 changed files with 13 additions and 8 deletions
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11
llvm/lib/CodeGen/RegAllocLocal.cpp
View File

@ -303,17 +303,12 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC); int FrameIndex = getStackSpaceFor(VirtReg, RC);
DOUT << " to stack slot #" << FrameIndex; DOUT << " to stack slot #" << FrameIndex;
TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
// If the instruction reads the register that's spilled, (e.g. this can // If the instruction reads the register that's spilled, (e.g. this can
// happen if it is a move to a physical register), then the spill // happen if it is a move to a physical register), then the spill
// instruction is not a kill. // instruction is not a kill.
if (I != MBB.end() && I->findRegisterUseOperandIdx(PhysReg) != -1) { bool isKill = !(I != MBB.end() &&
MachineBasicBlock::iterator StoreMI = prior(I); I->findRegisterUseOperandIdx(PhysReg) != -1);
int Idx = StoreMI->findRegisterUseOperandIdx(PhysReg, true); TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
assert(Idx != -1 && "Unrecognized spill instruction!");
StoreMI->getOperand(Idx).setIsKill(false);
}
++NumStores; // Update statistics ++NumStores; // Update statistics
} }

10
llvm/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll Normal file
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@ -0,0 +1,10 @@
; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -regalloc=local
define i32 @bork(i64 %foo, i64 %bar) {
entry:
%tmp = load i64* null, align 8 ; <i64> [#uses=2]
%tmp2 = icmp ule i64 %tmp, 0 ; <i1> [#uses=1]
%min = select i1 %tmp2, i64 %tmp, i64 0 ; <i64> [#uses=1]
store i64 %min, i64* null, align 8
ret i32 0
}