[AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

@@ -34,6 +34,7 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/IR/Constants.h"
+#include "llvm/IR/PatternMatch.h"
 #include "llvm/IR/Type.h"
 #include "llvm/IR/IntrinsicsAArch64.h"
 #include "llvm/Pass.h"
@@ -1739,6 +1740,17 @@ bool AArch64InstructionSelector::convertPtrAddToAdd(
     LLVM_DEBUG(dbgs() << "Failed to select G_PTRTOINT in convertPtrAddToAdd");
     return false;
   }
+
+  // Also take the opportunity here to try to do some optimization.
+  // Try to convert this into a G_SUB if the offset is a 0-x negate idiom.
+  Register NegatedReg;
+  int64_t Cst;
+  if (!mi_match(I.getOperand(2).getReg(), MRI,
+                m_GSub(m_ICst(Cst), m_Reg(NegatedReg))) ||
+      Cst != 0)
+    return true;
+  I.getOperand(2).setReg(NegatedReg);
+  I.setDesc(TII.get(TargetOpcode::G_SUB));
   return true;
 }
 

llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir

@@ -110,3 +110,22 @@ body:             |
     %ptr_add:gpr(p0) = G_PTR_ADD %ptr, %shift(s64)
     $x0 = COPY %ptr_add(p0)
 ...
+---
+name:            ptr_add_negated_reg
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0:
+      liveins: $x0, $x1
+    ; CHECK-LABEL: name: ptr_add_negated_reg
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK: %src:gpr64 = COPY $x1
+    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], %src, implicit-def $nzcv
+    ; CHECK: $x0 = COPY [[SUBSXrr]]
+    %0:gpr(p0) = COPY $x0
+    %src:gpr(s64) = COPY $x1
+    %1:gpr(s64) = G_CONSTANT i64 0
+    %neg:gpr(s64) = G_SUB %1, %src
+    %2:gpr(p0) = G_PTR_ADD %0, %neg(s64)
+    $x0 = COPY %2(p0)
+...