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[arm load/store optimizer] When trying to merge a base update load/store, make 

sure the base register and would-be writeback register don't conflict for
stores.  This was already being done for loads.

Unfortunately, it is rather difficult to create a test case for this issue.  It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://13394908>

llvm-svn: 177874
This commit is contained in:
Chad Rosier 2013-03-25 16:29:20 +00:00
parent 82050340c6
commit ace9c5dfaf
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -865,7 +865,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
// Can't do the merge if the destination register is the same as the would-be
// writeback register.
if (isLd && MI->getOperand(0).getReg() == Base)
if (MI->getOperand(0).getReg() == Base)
return false;
unsigned PredReg = 0;