forked from OSchip/llvm-project
ARM: Fix predefines (__ARM_ARCH_..., __REGISTER_PREFIX).
- This should be done leveraging the backend, but I'm a little refactored out. I'll fix it one day, I promise. llvm-svn: 91700
This commit is contained in:
Daniel Dunbar
parent
b48971d63f
commit
acde99ea52
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@ -56,6 +56,7 @@ def note_invalid_subexpr_in_ice : Note<
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def err_target_unknown_triple : Error<
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"unknown target triple '%0', please use -triple or -arch">;
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def err_target_unknown_cpu : Error<"unknown target CPU '%0'">;
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def err_target_unknown_abi : Error<"unknown target ABI '%0'">;
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def err_target_invalid_feature : Error<"invalid target feature '%0'">;
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@ -360,6 +360,15 @@ public:
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return "";
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}
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/// setCPU - Target the specific CPU.
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///
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/// \return - False on error (invalid CPU name).
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//
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// FIXME: Remove this.
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virtual bool setCPU(const std::string &Name) {
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return true;
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}
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/// setABI - Use the specific ABI.
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///
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/// \return - False on error (invalid ABI name).
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@ -1184,52 +1184,23 @@ public:
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namespace {
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class ARMTargetInfo : public TargetInfo {
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enum {
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Armv4t,
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Armv5,
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Armv6,
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Armv7a,
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XScale
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} ArmArch;
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static const TargetInfo::GCCRegAlias GCCRegAliases[];
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static const char * const GCCRegNames[];
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std::string ABI;
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std::string ABI, CPU;
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bool IsThumb;
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public:
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ARMTargetInfo(const std::string &TripleStr)
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: TargetInfo(TripleStr), ABI("aapcs-linux"), IsThumb(false)
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: TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s")
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{
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llvm::Triple Triple(TripleStr);
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SizeType = UnsignedInt;
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PtrDiffType = SignedInt;
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// FIXME: This shouldn't be done this way, we should use features to
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// indicate the arch. See lib/Driver/Tools.cpp.
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llvm::StringRef Version(""), Arch = Triple.getArchName();
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if (Arch.startswith("arm"))
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Version = Arch.substr(3);
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else if (Arch.startswith("thumb"))
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Version = Arch.substr(5);
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if (Version == "v7")
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ArmArch = Armv7a;
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else if (Version.empty() || Version == "v6" || Version == "v6t2")
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ArmArch = Armv6;
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else if (Version == "v5")
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ArmArch = Armv5;
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else if (Version == "v4t")
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ArmArch = Armv4t;
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else if (Arch == "xscale" || Arch == "thumbv5e")
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ArmArch = XScale;
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else
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ArmArch = Armv6;
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if (Arch.startswith("thumb"))
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IsThumb = true;
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// FIXME: Should we just treat this as a feature?
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IsThumb = Triple.getArchName().startswith("thumb");
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if (IsThumb) {
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DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
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"i64:64:64-f32:32:32-f64:64:64-"
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@ -1272,6 +1243,32 @@ public:
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return true;
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}
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static const char *getCPUDefineSuffix(llvm::StringRef Name) {
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return llvm::StringSwitch<const char*>(Name)
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.Cases("arm8", "arm810", "4")
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.Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
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.Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
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.Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
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.Case("ep9312", "4T")
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.Cases("arm10tdmi", "arm1020t", "5T")
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.Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
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.Case("arm926ej-s", "5TEJ")
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.Cases("arm10e", "arm1020e", "arm1022e", "5TE")
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.Cases("xscale", "iwmmxt", "5TE")
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.Cases("arm1136j-s", "arm1136jf-s", "6J")
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.Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
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.Cases("mpcorenovfp", "mpcore", "6K")
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.Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
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.Cases("cortex-a8", "cortex-a9", "7A")
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.Default(0);
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}
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virtual bool setCPU(const std::string &Name) {
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if (!getCPUDefineSuffix(Name))
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return false;
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CPU = Name;
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return true;
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}
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virtual void getTargetDefines(const LangOptions &Opts,
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std::vector<char> &Defs) const {
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// Target identification.
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@ -1279,37 +1276,39 @@ public:
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Define(Defs, "__arm__");
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// Target properties.
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Define(Defs, "__ARMEL__");
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Define(Defs, "__LITTLE_ENDIAN__");
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Define(Defs, "__REGISTER_PREFIX__", "");
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llvm::StringRef CPUArch = getCPUDefineSuffix(CPU);
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std::string ArchName = "__ARM_ARCH_";
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ArchName += CPUArch;
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ArchName += "__";
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Define(Defs, ArchName);
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// Subtarget options.
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//
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// FIXME: Neither THUMB_INTERWORK nor SOFTFP is not being set correctly
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// here.
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if (ArmArch == Armv7a) {
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Define(Defs, "__ARM_ARCH_7A__");
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Define(Defs, "__THUMB_INTERWORK__");
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} else if (ArmArch == Armv6) {
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Define(Defs, "__ARM_ARCH_6K__");
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Define(Defs, "__THUMB_INTERWORK__");
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} else if (ArmArch == Armv5) {
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Define(Defs, "__ARM_ARCH_5TEJ__");
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Define(Defs, "__THUMB_INTERWORK__");
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Define(Defs, "__SOFTFP__");
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} else if (ArmArch == Armv4t) {
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Define(Defs, "__ARM_ARCH_4T__");
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Define(Defs, "__SOFTFP__");
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} else if (ArmArch == XScale) {
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Define(Defs, "__ARM_ARCH_5TE__");
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Define(Defs, "__XSCALE__");
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Define(Defs, "__SOFTFP__");
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}
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Define(Defs, "__ARMEL__");
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// FIXME: It's more complicated than this and we don't really support
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// interworking.
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if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
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Define(Defs, "__THUMB_INTERWORK__");
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// FIXME: It's more complicated than this.
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if (ABI == "aapcs" || ABI == "aapcs-linux")
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Define(Defs, "__ARM_EABI__");
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// FIXME: This isn't correct, this should be set based on the various float
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// options.
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if (CPUArch[0] <= '5')
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Define(Defs, "__SOFTFP__");
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if (CPU == "xscale")
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Define(Defs, "__XSCALE__");
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if (IsThumb) {
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Define(Defs, "__THUMBEL__");
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Define(Defs, "__thumb__");
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if (ArmArch == Armv7a)
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if (CPUArch.startswith("7"))
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Define(Defs, "__thumb2__");
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}
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@ -2124,6 +2123,12 @@ TargetInfo *TargetInfo::CreateTargetInfo(Diagnostic &Diags,
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return 0;
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}
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// Set the target CPU if specified.
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if (!Opts.CPU.empty() && !Target->setCPU(Opts.CPU)) {
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Diags.Report(diag::err_target_unknown_cpu) << Opts.CPU;
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return 0;
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}
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// Set the target ABI if specified.
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if (!Opts.ABI.empty() && !Target->setABI(Opts.ABI)) {
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Diags.Report(diag::err_target_unknown_abi) << Opts.ABI;
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@ -118,7 +118,7 @@
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//
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// ARM:#define __APCS_32__ 1
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// ARM:#define __ARMEL__ 1
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// ARM:#define __ARM_ARCH_6K__ 1
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// ARM:#define __ARM_ARCH_6J__ 1
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// ARM:#define __CHAR_BIT__ 8
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// ARM:#define __DBL_DENORM_MIN__ 4.9406564584124654e-324
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// ARM:#define __DBL_DIG__ 15
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@ -180,6 +180,7 @@
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// ARM:#define __POINTER_WIDTH__ 32
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// ARM:#define __PTRDIFF_TYPE__ int
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// ARM:#define __PTRDIFF_WIDTH__ 32
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// ARM:#define __REGISTER_PREFIX__
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// ARM:#define __SCHAR_MAX__ 127
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// ARM:#define __SHRT_MAX__ 32767
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// ARM:#define __SIG_ATOMIC_WIDTH__ 32
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@ -836,7 +837,7 @@
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// SPARC:#define __POINTER_WIDTH__ 32
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// SPARC:#define __PTRDIFF_TYPE__ long int
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// SPARC:#define __PTRDIFF_WIDTH__ 32
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// SPARC:#define __REGISTER_PREFIX__
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// SPARC:#define __REGISTER_PREFIX__
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// SPARC:#define __SCHAR_MAX__ 127
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// SPARC:#define __SHRT_MAX__ 32767
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// SPARC:#define __SIG_ATOMIC_WIDTH__ 32
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