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[RISCV] Remove unused tablegen template parameters. NFC 

Identified in D109359
This commit is contained in:
Craig Topper 2021-09-08 10:01:29 -07:00
parent 6f1f30a957
commit aca14c8cf1
5 changed files with 25 additions and 39 deletions
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2
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
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@ -667,7 +667,7 @@ multiclass VCMP_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5,
Sched<[WriteVICmpI, ReadVICmpV, ReadVMask]>;
}
multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
Sched<[WriteVICmpV, ReadVICmpV, ReadVICmpV, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,

10
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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@ -2384,7 +2384,6 @@ class VPatTernaryNoMask<string intrinsic,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
@ -2407,7 +2406,6 @@ class VPatTernaryNoMaskWithPolicy<string intrinsic,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
@ -3014,8 +3012,8 @@ multiclass VPatTernary<string intrinsic,
RegisterClass op1_reg_class,
DAGOperand op2_kind> {
def : VPatTernaryNoMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;
sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;
def : VPatTernaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;
@ -3034,8 +3032,8 @@ multiclass VPatTernaryWithPolicy<string intrinsic,
RegisterClass op1_reg_class,
DAGOperand op2_kind> {
def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type,
op2_type, mask_type, sew, vlmul,
result_reg_class, op1_reg_class, op2_kind>;
op2_type, sew, vlmul, result_reg_class,
op1_reg_class, op2_kind>;
def : VPatTernaryMask<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>;

26
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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@ -103,11 +103,9 @@ class VPatBinarySDNode_VV<SDNode vop,
string instruction_name,
ValueType result_type,
ValueType op_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
OutPatFrag avl,
VReg RetClass,
VReg op_reg_class> :
Pat<(result_type (vop
(op_type op_reg_class:$rs1),
@ -122,11 +120,9 @@ class VPatBinarySDNode_XI<SDNode vop,
string suffix,
ValueType result_type,
ValueType vop_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
OutPatFrag avl,
VReg RetClass,
VReg vop_reg_class,
ComplexPattern SplatPatKind,
DAGOperand xop_kind> :
@ -141,11 +137,11 @@ class VPatBinarySDNode_XI<SDNode vop,
multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name> {
foreach vti = AllIntegerVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass>;
def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass,
SplatPat, GPR>;
}
}
@ -155,8 +151,8 @@ multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
: VPatBinarySDNode_VV_VX<vop, instruction_name> {
foreach vti = AllIntegerVectors in {
def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass,
!cast<ComplexPattern>(SplatPat#_#ImmType),
ImmType>;
}
@ -167,11 +163,9 @@ class VPatBinarySDNode_VF<SDNode vop,
ValueType result_type,
ValueType vop_type,
ValueType xop_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
OutPatFrag avl,
VReg RetClass,
VReg vop_reg_class,
DAGOperand xop_kind> :
Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
@ -184,11 +178,11 @@ class VPatBinarySDNode_VF<SDNode vop,
multiclass VPatBinaryFPSDNode_VV_VF<SDNode vop, string instruction_name> {
foreach vti = AllFloatVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
vti.Vector, vti.Vector, vti.Log2SEW,
vti.LMul, vti.AVL, vti.RegClass>;
def : VPatBinarySDNode_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,
vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
vti.Vector, vti.Vector, vti.Scalar,
vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
vti.ScalarRegClass>;
}
}

20
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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@ -273,7 +273,6 @@ multiclass VPatBinaryVL_VV<SDNode vop,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg RetClass,
VReg op_reg_class> {
def : Pat<(result_type (vop
(op_type op_reg_class:$rs1),
@ -304,7 +303,6 @@ multiclass VPatBinaryVL_XI<SDNode vop,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg RetClass,
VReg vop_reg_class,
ComplexPattern SplatPatKind,
DAGOperand xop_kind> {
@ -333,11 +331,10 @@ multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> {
foreach vti = AllIntegerVectors in {
defm : VPatBinaryVL_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass>;
vti.LMul, vti.RegClass>;
defm : VPatBinaryVL_XI<vop, instruction_name, "VX",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass,
SplatPat, GPR>;
vti.LMul, vti.RegClass, SplatPat, GPR>;
}
}
@ -347,7 +344,7 @@ multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name,
foreach vti = AllIntegerVectors in {
defm : VPatBinaryVL_XI<vop, instruction_name, "VI",
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass,
vti.LMul, vti.RegClass,
!cast<ComplexPattern>(SplatPat#_#ImmType),
ImmType>;
}
@ -359,11 +356,10 @@ multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> {
defvar wti = VtiToWti.Wti;
defm : VPatBinaryVL_VV<vop, instruction_name,
wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, wti.RegClass, vti.RegClass>;
vti.LMul, vti.RegClass>;
defm : VPatBinaryVL_XI<vop, instruction_name, "VX",
wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, wti.RegClass, vti.RegClass,
SplatPat, GPR>;
vti.LMul, vti.RegClass, SplatPat, GPR>;
}
}
@ -374,7 +370,6 @@ class VPatBinaryVL_VF<SDNode vop,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg RetClass,
VReg vop_reg_class,
RegisterClass scalar_reg_class> :
Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
@ -390,11 +385,10 @@ multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> {
foreach vti = AllFloatVectors in {
defm : VPatBinaryVL_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass>;
vti.LMul, vti.RegClass>;
def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,
vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
vti.LMul, vti.RegClass, vti.RegClass,
vti.ScalarRegClass>;
vti.LMul, vti.RegClass, vti.ScalarRegClass>;
}
}

6
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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@ -372,7 +372,7 @@ class NFList<int lmul> {
}
// Generate [start, end) SubRegIndex list.
class SubRegSet<list<SubRegIndex> LIn, int start, int nf, int lmul> {
class SubRegSet<int nf, int lmul> {
list<SubRegIndex> L = !foldl([]<SubRegIndex>,
[0, 1, 2, 3, 4, 5, 6, 7],
AccList, i,
@ -463,10 +463,10 @@ let RegAltNameIndices = [ABIRegAltName] in {
foreach m = [1, 2, 4] in {
foreach n = NFList<m>.L in {
def "VN" # n # "M" # m # "NoV0": RegisterTuples<
SubRegSet<[], 0, n, m>.L,
SubRegSet<n, m>.L,
VRegList<[], 0, n, m, 1>.L>;
def "VN" # n # "M" # m # "V0" : RegisterTuples<
SubRegSet<[], 0, n, m>.L,
SubRegSet<n, m>.L,
VRegList<[], 0, n, m, 0>.L>;
}
}