forked from OSchip/llvm-project
[AMDGPU] Fix failure in VCC spilling
Spills of VCC (SGPR64) will fail with new SGPR spill code, because super register is not correctly resolved. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D81224
This commit is contained in:
Carl Ritson
parent
547b6da73c
commit
ac8a2f132b
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@ -938,12 +938,12 @@ void SIRegisterInfo::buildSGPRSpillLoadStore(MachineBasicBlock::iterator MI,
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} else {
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} else {
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SavedExecReg =
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SavedExecReg =
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getMatchingSuperReg(getSubReg(SuperReg, SplitParts[FirstPart]),
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getMatchingSuperReg(getSubReg(SuperReg, SplitParts[FirstPart]),
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AMDGPU::sub0, &AMDGPU::SGPR_64RegClass);
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AMDGPU::sub0, &AMDGPU::SReg_64_XEXECRegClass);
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// If src/dst is an odd size it is possible subreg0 is not aligned.
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// If src/dst is an odd size it is possible subreg0 is not aligned.
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if (!SavedExecReg && NumSubRegs > 2)
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if (!SavedExecReg && NumSubRegs > 2)
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SavedExecReg =
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SavedExecReg =
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getMatchingSuperReg(getSubReg(SuperReg, SplitParts[FirstPart + 1]),
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getMatchingSuperReg(getSubReg(SuperReg, SplitParts[FirstPart + 1]),
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AMDGPU::sub0, &AMDGPU::SGPR_64RegClass);
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AMDGPU::sub0, &AMDGPU::SReg_64_XEXECRegClass);
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}
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}
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assert(SavedExecReg);
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assert(SavedExecReg);
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@ -0,0 +1,181 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GFX9 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GFX10 %s
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--- |
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define amdgpu_kernel void @check_vcc() #0 {
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ret void
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}
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define amdgpu_kernel void @check_exec() #0 {
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ret void
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}
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attributes #0 = { "frame-pointer"="all" }
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...
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---
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name: check_vcc
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr4_sgpr5' }
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- { reg: '$sgpr6_sgpr7' }
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- { reg: '$sgpr8' }
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 8, alignment: 4 }
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machineFunctionInfo:
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isEntryFunction: true
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waveLimiter: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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dispatchPtr: { reg: '$sgpr4_sgpr5' }
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kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
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workGroupIDX: { reg: '$sgpr8' }
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privateSegmentWaveByteOffset: { reg: '$sgpr9' }
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body: |
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bb.0:
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liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7
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; CHECK-LABEL: name: check_vcc
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; CHECK: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9
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; GFX9: $sgpr33 = S_MOV_B32 0
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; GFX9: $sgpr12 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr13 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr14 = S_MOV_B32 4294967295, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr15 = S_MOV_B32 14680064, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $vcc = IMPLICIT_DEF
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $vcc_lo, 0, undef $vgpr0, implicit $vcc
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $vcc_hi, 1, $vgpr0, implicit $vcc
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $exec_lo, 32, $vgpr0
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $exec_hi, 33, $vgpr0
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; GFX9: $exec = S_MOV_B64 3
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; GFX9: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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; GFX9: $exec_lo = V_READLANE_B32_vi $vgpr0, 32
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; GFX9: $exec_hi = V_READLANE_B32_vi killed $vgpr0, 33
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; GFX9: $vcc = IMPLICIT_DEF
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $vcc_lo, 0, undef $vgpr0, implicit $vcc
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $vcc_hi, 1, $vgpr0, implicit killed $vcc
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; GFX9: $vcc = S_MOV_B64 $exec
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; GFX9: $exec = S_MOV_B64 3
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; GFX9: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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; GFX9: $exec = S_MOV_B64 killed $vcc
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; GFX9: $vcc = S_MOV_B64 $exec
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; GFX9: $exec = S_MOV_B64 3
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; GFX9: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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; GFX9: $exec = S_MOV_B64 killed $vcc
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; GFX9: $vcc_lo = V_READLANE_B32_vi $vgpr0, 0, implicit-def $vcc
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; GFX9: $vcc_hi = V_READLANE_B32_vi killed $vgpr0, 1
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; GFX10: $sgpr33 = S_MOV_B32 0
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; GFX10: $sgpr96 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr97 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr98 = S_MOV_B32 4294967295, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr99 = S_MOV_B32 836853760, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr96 = S_ADD_U32 $sgpr96, $sgpr9, implicit-def $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr97 = S_ADDC_U32 $sgpr97, 0, implicit-def $scc, implicit $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $vcc = IMPLICIT_DEF
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $vcc_lo, 0, undef $vgpr0, implicit $vcc
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $vcc_hi, 1, $vgpr0, implicit $vcc
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $exec_lo, 32, $vgpr0
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $exec_hi, 33, $vgpr0
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; GFX10: $exec = S_MOV_B64 3
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; GFX10: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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; GFX10: $exec_lo = V_READLANE_B32_gfx10 $vgpr0, 32
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; GFX10: $exec_hi = V_READLANE_B32_gfx10 killed $vgpr0, 33
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; GFX10: $vcc = IMPLICIT_DEF
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $vcc_lo, 0, undef $vgpr0, implicit $vcc
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $vcc_hi, 1, $vgpr0, implicit killed $vcc
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; GFX10: $vcc = S_MOV_B64 $exec
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; GFX10: $exec = S_MOV_B64 3
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; GFX10: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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; GFX10: $exec = S_MOV_B64 killed $vcc
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; GFX10: $vcc = S_MOV_B64 $exec
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; GFX10: $exec = S_MOV_B64 3
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; GFX10: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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; GFX10: $exec = S_MOV_B64 killed $vcc
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; GFX10: $vcc_lo = V_READLANE_B32_gfx10 $vgpr0, 0, implicit-def $vcc
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; GFX10: $vcc_hi = V_READLANE_B32_gfx10 killed $vgpr0, 1
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$vcc = IMPLICIT_DEF
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SI_SPILL_S64_SAVE $vcc, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
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$vcc = IMPLICIT_DEF
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SI_SPILL_S64_SAVE killed $vcc, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
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$vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
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...
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---
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name: check_exec
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tracksRegLiveness: true
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liveins:
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- { reg: '$sgpr4_sgpr5' }
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- { reg: '$sgpr6_sgpr7' }
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- { reg: '$sgpr8' }
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 8, alignment: 4 }
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machineFunctionInfo:
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isEntryFunction: true
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waveLimiter: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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dispatchPtr: { reg: '$sgpr4_sgpr5' }
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kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
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workGroupIDX: { reg: '$sgpr8' }
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privateSegmentWaveByteOffset: { reg: '$sgpr9' }
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body: |
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bb.0:
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liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7
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; CHECK-LABEL: name: check_exec
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; CHECK: liveins: $sgpr8, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9
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; GFX9: $sgpr33 = S_MOV_B32 0
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; GFX9: $sgpr12 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr13 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr14 = S_MOV_B32 4294967295, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr15 = S_MOV_B32 14680064, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $exec_lo, 0, undef $vgpr0, implicit $exec
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; GFX9: $vgpr0 = V_WRITELANE_B32_vi $exec_hi, 1, $vgpr0, implicit $exec
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; GFX9: $exec = S_MOV_B64 3
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; GFX9: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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; GFX9: $exec_lo = V_READLANE_B32_vi $vgpr0, 0
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; GFX9: $exec_hi = V_READLANE_B32_vi killed $vgpr0, 1
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; GFX9: $exec = S_MOV_B64 3
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; GFX9: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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; GFX9: $exec_lo = V_READLANE_B32_vi $vgpr0, 0, implicit-def $exec
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; GFX9: $exec_hi = V_READLANE_B32_vi killed $vgpr0, 1
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; GFX10: $sgpr33 = S_MOV_B32 0
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; GFX10: $sgpr96 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr97 = S_MOV_B32 &SCRATCH_RSRC_DWORD1, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr98 = S_MOV_B32 4294967295, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr99 = S_MOV_B32 836853760, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr96 = S_ADD_U32 $sgpr96, $sgpr9, implicit-def $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $sgpr97 = S_ADDC_U32 $sgpr97, 0, implicit-def $scc, implicit $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $exec_lo, 0, undef $vgpr0, implicit $exec
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; GFX10: $vgpr0 = V_WRITELANE_B32_gfx10 $exec_hi, 1, $vgpr0, implicit $exec
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; GFX10: $exec = S_MOV_B64 3
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; GFX10: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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; GFX10: $exec_lo = V_READLANE_B32_gfx10 $vgpr0, 0
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; GFX10: $exec_hi = V_READLANE_B32_gfx10 killed $vgpr0, 1
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; GFX10: $exec = S_MOV_B64 3
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; GFX10: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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; GFX10: $exec_lo = V_READLANE_B32_gfx10 $vgpr0, 0, implicit-def $exec
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; GFX10: $exec_hi = V_READLANE_B32_gfx10 killed $vgpr0, 1
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SI_SPILL_S64_SAVE $exec, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
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$exec = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32
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...
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