forked from OSchip/llvm-project
[OMPIRBuilder] Add support for simdlen clause
This patch adds OMPIRBuilder support for the simdlen clause for the simd directive. It uses the simdlen support in OpenMPIRBuilder when it is enabled in Clang. Simdlen is lowered by OpenMPIRBuilder by generating the loop.vectorize.width metadata. Reviewed By: jdoerfert, Meinersbur Differential Revision: https://reviews.llvm.org/D129149
This commit is contained in:
Prabhdeep Singh Soni
Arnamoy Bhattacharyya
parent
6e8e91a7b6
commit
ac892c70a4
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@ -2591,11 +2591,12 @@ static void emitOMPSimdRegion(CodeGenFunction &CGF, const OMPLoopDirective &S,
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}
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}
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static bool isSupportedByOpenMPIRBuilder(const OMPExecutableDirective &S) {
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static bool isSupportedByOpenMPIRBuilder(const OMPSimdDirective &S) {
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// Check for unsupported clauses
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if (!S.clauses().empty()) {
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// Currently no clause is supported
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return false;
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for (OMPClause *C : S.clauses()) {
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// Currently only simdlen clause is supported
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if (!isa<OMPSimdlenClause>(C))
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return false;
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}
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// Check if we have a statement with the ordered directive.
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@ -2630,7 +2631,6 @@ void CodeGenFunction::EmitOMPSimdDirective(const OMPSimdDirective &S) {
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// Use the OpenMPIRBuilder if enabled.
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if (UseOMPIRBuilder) {
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// Emit the associated statement and get its loop representation.
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llvm::DebugLoc DL = SourceLocToDebugLoc(S.getBeginLoc());
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const Stmt *Inner = S.getRawStmt();
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llvm::CanonicalLoopInfo *CLI =
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EmitOMPCollapsedCanonicalLoopNest(Inner, 1);
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@ -2638,7 +2638,15 @@ void CodeGenFunction::EmitOMPSimdDirective(const OMPSimdDirective &S) {
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llvm::OpenMPIRBuilder &OMPBuilder =
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CGM.getOpenMPRuntime().getOMPBuilder();
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// Add SIMD specific metadata
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OMPBuilder.applySimd(DL, CLI);
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llvm::ConstantInt *Simdlen = nullptr;
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if (const auto *C = S.getSingleClause<OMPSimdlenClause>()) {
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RValue Len =
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this->EmitAnyExpr(C->getSimdlen(), AggValueSlot::ignored(),
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/*ignoreResult=*/true);
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auto *Val = cast<llvm::ConstantInt>(Len.getScalarVal());
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Simdlen = Val;
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}
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OMPBuilder.applySimd(CLI, Simdlen);
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return;
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}
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};
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@ -68,4 +68,4 @@ void simple(float *a, float *b, int *c) {
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// CHECK-NEXT: ![[META6]] = !{!"llvm.loop.vectorize.enable", i1 true}
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// CHECK-NEXT: ![[META7:[0-9]+]] = distinct !{}
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// CHECK-NEXT: ![[META8]] = distinct !{![[META8]], ![[META9:[0-9]+]], ![[META6]]}
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// CHECK-NEXT: ![[META9]] = !{!"llvm.loop.parallel_accesses", ![[META7]]}
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// CHECK-NEXT: ![[META9]] = !{!"llvm.loop.parallel_accesses", ![[META7]]}
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@ -0,0 +1,139 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-enable-irbuilder -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
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// expected-no-diagnostics
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struct S {
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int a, b;
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};
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struct P {
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int a, b;
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};
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// CHECK-LABEL: @_Z6simplePfS_Pi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8
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// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32*, align 8
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// CHECK-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 4
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// CHECK-NEXT: [[P:%.*]] = alloca %struct.S*, align 8
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// CHECK-NEXT: [[PP:%.*]] = alloca [[STRUCT_P:%.*]], align 4
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// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
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// CHECK-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 4
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// CHECK-NEXT: [[DOTCOUNT_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
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// CHECK-NEXT: [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 4
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// CHECK-NEXT: [[DOTCOUNT_ADDR10:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store float* [[A:%.*]], float** [[A_ADDR]], align 8
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// CHECK-NEXT: store float* [[B:%.*]], float** [[B_ADDR]], align 8
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// CHECK-NEXT: store i32* [[C:%.*]], i32** [[C_ADDR]], align 8
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// CHECK-NEXT: store i32 3, i32* [[I]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
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// CHECK-NEXT: store i32* [[I]], i32** [[TMP0]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[AGG_CAPTURED1]], i32 0, i32 0
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// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
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// CHECK-NEXT: store i32 [[TMP2]], i32* [[TMP1]], align 4
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// CHECK-NEXT: call void @__captured_stmt(i32* [[DOTCOUNT_ADDR]], %struct.anon* [[AGG_CAPTURED]])
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// CHECK-NEXT: [[DOTCOUNT:%.*]] = load i32, i32* [[DOTCOUNT_ADDR]], align 4
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// CHECK-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
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// CHECK: omp_loop.preheader:
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER:%.*]]
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// CHECK: omp_loop.header:
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// CHECK-NEXT: [[OMP_LOOP_IV:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER]] ], [ [[OMP_LOOP_NEXT:%.*]], [[OMP_LOOP_INC:%.*]] ]
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// CHECK-NEXT: br label [[OMP_LOOP_COND:%.*]]
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// CHECK: omp_loop.cond:
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// CHECK-NEXT: [[OMP_LOOP_CMP:%.*]] = icmp ult i32 [[OMP_LOOP_IV]], [[DOTCOUNT]]
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// CHECK-NEXT: br i1 [[OMP_LOOP_CMP]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_LOOP_EXIT:%.*]]
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// CHECK: omp_loop.body:
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// CHECK-NEXT: call void @__captured_stmt.1(i32* [[I]], i32 [[OMP_LOOP_IV]], %struct.anon.0* [[AGG_CAPTURED1]]), !llvm.access.group [[ACC_GRP3:![0-9]+]]
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// CHECK-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
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// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]]
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// CHECK-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[S]], i32 0, i32 0
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// CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[A2]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP6]] to float
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// CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP5]], [[CONV]]
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// CHECK-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[P]], align 8, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP7]], i32 0, i32 0
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// CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[A3]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP8]] to float
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// CHECK-NEXT: [[ADD5:%.*]] = fadd float [[ADD]], [[CONV4]]
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// CHECK-NEXT: [[TMP9:%.*]] = load float*, float** [[A_ADDR]], align 8, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP10]] to i64
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// CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM6]]
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// CHECK-NEXT: store float [[ADD5]], float* [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]]
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// CHECK-NEXT: br label [[OMP_LOOP_INC]]
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// CHECK: omp_loop.inc:
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// CHECK-NEXT: [[OMP_LOOP_NEXT]] = add nuw i32 [[OMP_LOOP_IV]], 1
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]]
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// CHECK: omp_loop.exit:
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// CHECK-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
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// CHECK: omp_loop.after:
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// CHECK-NEXT: store i32 3, i32* [[J]], align 4
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// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED8]], i32 0, i32 0
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// CHECK-NEXT: store i32* [[J]], i32** [[TMP11]], align 8
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// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[AGG_CAPTURED9]], i32 0, i32 0
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// CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[J]], align 4
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// CHECK-NEXT: store i32 [[TMP13]], i32* [[TMP12]], align 4
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// CHECK-NEXT: call void @__captured_stmt.2(i32* [[DOTCOUNT_ADDR10]], %struct.anon.1* [[AGG_CAPTURED8]])
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// CHECK-NEXT: [[DOTCOUNT11:%.*]] = load i32, i32* [[DOTCOUNT_ADDR10]], align 4
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// CHECK-NEXT: br label [[OMP_LOOP_PREHEADER12:%.*]]
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// CHECK: omp_loop.preheader12:
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER13:%.*]]
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// CHECK: omp_loop.header13:
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// CHECK-NEXT: [[OMP_LOOP_IV19:%.*]] = phi i32 [ 0, [[OMP_LOOP_PREHEADER12]] ], [ [[OMP_LOOP_NEXT21:%.*]], [[OMP_LOOP_INC16:%.*]] ]
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// CHECK-NEXT: br label [[OMP_LOOP_COND14:%.*]]
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// CHECK: omp_loop.cond14:
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// CHECK-NEXT: [[OMP_LOOP_CMP20:%.*]] = icmp ult i32 [[OMP_LOOP_IV19]], [[DOTCOUNT11]]
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// CHECK-NEXT: br i1 [[OMP_LOOP_CMP20]], label [[OMP_LOOP_BODY15:%.*]], label [[OMP_LOOP_EXIT17:%.*]]
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// CHECK: omp_loop.body15:
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// CHECK-NEXT: call void @__captured_stmt.3(i32* [[J]], i32 [[OMP_LOOP_IV19]], %struct.anon.2* [[AGG_CAPTURED9]]), !llvm.access.group [[ACC_GRP8:![0-9]+]]
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// CHECK-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_P]], %struct.P* [[PP]], i32 0, i32 0
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// CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[A22]], align 4, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: [[TMP15:%.*]] = load i32*, i32** [[C_ADDR]], align 8, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[J]], align 4, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: [[IDXPROM23:%.*]] = sext i32 [[TMP16]] to i64
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// CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i64 [[IDXPROM23]]
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// CHECK-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX24]], align 4, !llvm.access.group [[ACC_GRP8]]
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// CHECK-NEXT: br label [[OMP_LOOP_INC16]]
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// CHECK: omp_loop.inc16:
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// CHECK-NEXT: [[OMP_LOOP_NEXT21]] = add nuw i32 [[OMP_LOOP_IV19]], 1
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// CHECK-NEXT: br label [[OMP_LOOP_HEADER13]], !llvm.loop [[LOOP9:![0-9]+]]
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// CHECK: omp_loop.exit17:
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// CHECK-NEXT: br label [[OMP_LOOP_AFTER18:%.*]]
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// CHECK: omp_loop.after18:
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// CHECK-NEXT: ret void
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//
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void simple(float *a, float *b, int *c) {
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S s, *p;
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P pp;
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#pragma omp simd simdlen(3)
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for (int i = 3; i < 32; i += 5) {
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a[i] = b[i] + s.a + p->a;
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}
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#pragma omp simd
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for (int j = 3; j < 32; j += 5) {
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c[j] = pp.a;
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}
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}
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//.
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// CHECK: attributes #0 = { mustprogress noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
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// CHECK: attributes #1 = { noinline nounwind optnone "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" }
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//.
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// CHECK: !0 = !{i32 1, !"wchar_size", i32 4}
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// CHECK: !1 = !{i32 7, !"openmp", i32 45}
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// CHECK: !3 = distinct !{}
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// CHECK: !4 = distinct !{!4, !5, !6, !7}
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// CHECK: !5 = !{!"llvm.loop.parallel_accesses", !3}
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// CHECK: !6 = !{!"llvm.loop.vectorize.enable", i1 true}
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// CHECK: !7 = !{!"llvm.loop.vectorize.width", i32 3}
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// CHECK: !8 = distinct !{}
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// CHECK: !9 = distinct !{!9, !10, !6}
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// CHECK: !10 = !{!"llvm.loop.parallel_accesses", !8}
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//.
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@ -599,9 +599,9 @@ public:
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/// Add metadata to simd-ize a loop.
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///
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/// \param DL Debug location for instructions added by unrolling.
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/// \param Loop The loop to simd-ize.
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void applySimd(DebugLoc DL, CanonicalLoopInfo *Loop);
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/// \param Loop The loop to simd-ize.
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/// \param Simdlen The Simdlen length to apply to the simd loop.
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void applySimd(CanonicalLoopInfo *Loop, ConstantInt *Simdlen);
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/// Generator for '#omp flush'
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///
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@ -2866,7 +2866,8 @@ void OpenMPIRBuilder::unrollLoopHeuristic(DebugLoc, CanonicalLoopInfo *Loop) {
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});
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}
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void OpenMPIRBuilder::applySimd(DebugLoc, CanonicalLoopInfo *CanonicalLoop) {
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void OpenMPIRBuilder::applySimd(CanonicalLoopInfo *CanonicalLoop,
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ConstantInt *Simdlen) {
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LLVMContext &Ctx = Builder.getContext();
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Function *F = CanonicalLoop->getFunction();
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@ -2911,6 +2912,11 @@ void OpenMPIRBuilder::applySimd(DebugLoc, CanonicalLoopInfo *CanonicalLoop) {
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AccessGroup}),
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MDNode::get(Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.enable"),
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BoolConst})});
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if (Simdlen != nullptr)
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addLoopMetadata(
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CanonicalLoop,
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MDNode::get(Ctx, {MDString::get(Ctx, "llvm.loop.vectorize.width"),
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ConstantAsMetadata::get(Simdlen)}));
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}
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/// Create the TargetMachine object to query the backend for optimization
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@ -1769,7 +1769,7 @@ TEST_F(OpenMPIRBuilderTest, ApplySimd) {
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CanonicalLoopInfo *CLI = buildSingleLoopFunction(DL, OMPBuilder, 32);
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// Simd-ize the loop.
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OMPBuilder.applySimd(DL, CLI);
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OMPBuilder.applySimd(CLI, nullptr);
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OMPBuilder.finalize();
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EXPECT_FALSE(verifyModule(*M, &errs()));
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@ -1794,6 +1794,38 @@ TEST_F(OpenMPIRBuilderTest, ApplySimd) {
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}));
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}
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TEST_F(OpenMPIRBuilderTest, ApplySimdlen) {
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OpenMPIRBuilder OMPBuilder(*M);
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CanonicalLoopInfo *CLI = buildSingleLoopFunction(DL, OMPBuilder, 32);
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// Simd-ize the loop.
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OMPBuilder.applySimd(CLI, ConstantInt::get(Type::getInt32Ty(Ctx), 3));
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OMPBuilder.finalize();
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EXPECT_FALSE(verifyModule(*M, &errs()));
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PassBuilder PB;
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FunctionAnalysisManager FAM;
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PB.registerFunctionAnalyses(FAM);
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LoopInfo &LI = FAM.getResult<LoopAnalysis>(*F);
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const std::vector<Loop *> &TopLvl = LI.getTopLevelLoops();
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EXPECT_EQ(TopLvl.size(), 1u);
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Loop *L = TopLvl.front();
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EXPECT_TRUE(findStringMetadataForLoop(L, "llvm.loop.parallel_accesses"));
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EXPECT_TRUE(getBooleanLoopAttribute(L, "llvm.loop.vectorize.enable"));
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EXPECT_EQ(getIntLoopAttribute(L, "llvm.loop.vectorize.width"), 3);
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// Check for llvm.access.group metadata attached to the printf
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// function in the loop body.
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BasicBlock *LoopBody = CLI->getBody();
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EXPECT_TRUE(any_of(*LoopBody, [](Instruction &I) {
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return I.getMetadata("llvm.access.group") != nullptr;
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}));
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}
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TEST_F(OpenMPIRBuilderTest, UnrollLoopFull) {
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OpenMPIRBuilder OMPBuilder(*M);
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@ -719,18 +719,19 @@ class NamelessValue:
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# Description of the different "unnamed" values we match in the IR, e.g.,
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# (local) ssa values, (debug) metadata, etc.
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ir_nameless_values = [
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NamelessValue(r'TMP' , '%' , r'%' , None , None , r'[\w$.-]+?' , None , False) ,
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NamelessValue(r'ATTR' , '#' , r'#' , None , None , r'[0-9]+' , None , False) ,
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NamelessValue(r'ATTR' , '#' , None , r'attributes #' , r'[0-9]+' , None , r'{[^}]*}' , False) ,
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NamelessValue(r'GLOB' , '@' , r'@' , None , None , r'[0-9]+' , None , False) ,
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NamelessValue(r'GLOB' , '@' , None , r'@' , r'[a-zA-Z0-9_$"\\.-]+' , None , r'.+' , True) ,
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NamelessValue(r'DBG' , '!' , r'!dbg ' , None , None , r'![0-9]+' , None , False) ,
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NamelessValue(r'PROF' , '!' , r'!prof ' , None , None , r'![0-9]+' , None , False) ,
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NamelessValue(r'TBAA' , '!' , r'!tbaa ' , None , None , r'![0-9]+' , None , False) ,
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NamelessValue(r'RNG' , '!' , r'!range ' , None , None , r'![0-9]+' , None , False) ,
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NamelessValue(r'LOOP' , '!' , r'!llvm.loop ' , None , None , r'![0-9]+' , None , False) ,
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NamelessValue(r'META' , '!' , r'metadata ' , None , None , r'![0-9]+' , None , False) ,
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NamelessValue(r'META' , '!' , None , r'' , r'![0-9]+' , None , r'(?:distinct |)!.*' , False) ,
|
||||
NamelessValue(r'TMP' , '%' , r'%' , None , None , r'[\w$.-]+?' , None , False) ,
|
||||
NamelessValue(r'ATTR' , '#' , r'#' , None , None , r'[0-9]+' , None , False) ,
|
||||
NamelessValue(r'ATTR' , '#' , None , r'attributes #' , r'[0-9]+' , None , r'{[^}]*}' , False) ,
|
||||
NamelessValue(r'GLOB' , '@' , r'@' , None , None , r'[0-9]+' , None , False) ,
|
||||
NamelessValue(r'GLOB' , '@' , None , r'@' , r'[a-zA-Z0-9_$"\\.-]+' , None , r'.+' , True) ,
|
||||
NamelessValue(r'DBG' , '!' , r'!dbg ' , None , None , r'![0-9]+' , None , False) ,
|
||||
NamelessValue(r'PROF' , '!' , r'!prof ' , None , None , r'![0-9]+' , None , False) ,
|
||||
NamelessValue(r'TBAA' , '!' , r'!tbaa ' , None , None , r'![0-9]+' , None , False) ,
|
||||
NamelessValue(r'RNG' , '!' , r'!range ' , None , None , r'![0-9]+' , None , False) ,
|
||||
NamelessValue(r'LOOP' , '!' , r'!llvm.loop ' , None , None , r'![0-9]+' , None , False) ,
|
||||
NamelessValue(r'META' , '!' , r'metadata ' , None , None , r'![0-9]+' , None , False) ,
|
||||
NamelessValue(r'META' , '!' , None , r'' , r'![0-9]+' , None , r'(?:distinct |)!.*' , False) ,
|
||||
NamelessValue(r'ACC_GRP' , '!' , r'!llvm.access.group ' , None , None , r'![0-9]+' , None , False) ,
|
||||
]
|
||||
|
||||
asm_nameless_values = [
|
||||
|
|
|
|||
|
|
@ -971,7 +971,7 @@ convertOmpSimdLoop(Operation &opInst, llvm::IRBuilderBase &builder,
|
|||
llvm::CanonicalLoopInfo *loopInfo =
|
||||
ompBuilder->collapseLoops(ompLoc.DL, loopInfos, {});
|
||||
|
||||
ompBuilder->applySimd(ompLoc.DL, loopInfo);
|
||||
ompBuilder->applySimd(loopInfo, nullptr);
|
||||
|
||||
builder.restoreIP(afterIP);
|
||||
return success();
|
||||
|
|
|
|||
Loading…
Reference in New Issue