forked from OSchip/llvm-project
[PowerPC] More precise exploitation of P9 maddld instruction when operands are constant
There are 3 operands of maddld, (add (mul %1, %2), %3) and sometimes they are constant. If there is constant operand, it takes extra li to materialize the operand, and one more extra register too. So it's not profitable to use maddld to optimize mul-add pattern. Differential Revision: https://reviews.llvm.org/D60181 llvm-svn: 358253
This commit is contained in:
Zi Xuan Wu
parent
aa1cad1591
commit
ac79ef8f0e
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@ -777,7 +777,7 @@ def MADDHDU : VAForm_1a<49,
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"maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64;
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def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC),
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"maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
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[(set i32:$RT, (add (mul i32:$RA, i32:$RB), i32:$RC))]>,
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[(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>,
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isPPC64;
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def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA),
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"setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
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@ -785,7 +785,7 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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def MADDLD8 : VAForm_1a<51,
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(outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
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"maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
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[(set i64:$RT, (add (mul i64:$RA, i64:$RB), i64:$RC))]>,
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[(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
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isPPC64;
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def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
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"setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
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@ -457,6 +457,17 @@ def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr),
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return !isOffsetMultipleOf(N, 16);
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}]>;
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// PatFrag for binary operation whose operands are both non-constant
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class BinOpWithoutSImm16Operand<SDNode opcode> :
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PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{
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int16_t Imm;
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return !isIntS16Immediate(N->getOperand(0), Imm)
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&& !isIntS16Immediate(N->getOperand(1), Imm);
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}]>;
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def add_without_simm16 : BinOpWithoutSImm16Operand<add>;
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def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>;
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//===----------------------------------------------------------------------===//
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// PowerPC Flag Definitions.
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@ -1,18 +1,15 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P9
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P8
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P9
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P8
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define signext i64 @maddld64(i64 signext %a, i64 signext %b) {
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; CHECK-P9-LABEL: maddld64:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-LABEL: maddld64:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: maddld64:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: mulld 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-P8-NEXT: blr
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; CHECK-NEXT: blr
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entry:
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%mul = mul i64 %b, %a
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%add = add i64 %mul, %a
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@ -20,18 +17,15 @@ entry:
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}
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define signext i32 @maddld32(i32 signext %a, i32 signext %b) {
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; CHECK-P9-LABEL: maddld32:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-LABEL: maddld32:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P9-NEXT: extsw 3, 3
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: maddld32:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-P8-NEXT: extsw 3, 3
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; CHECK-P8-NEXT: blr
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, %a
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@ -39,18 +33,15 @@ entry:
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}
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define signext i16 @maddld16(i16 signext %a, i16 signext %b, i16 signext %c) {
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; CHECK-P9-LABEL: maddld16:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-LABEL: maddld16:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 5
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; CHECK-P9-NEXT: extsh 3, 3
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: maddld16:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: mullw 3, 4, 3
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; CHECK-P8-NEXT: add 3, 3, 5
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; CHECK-P8-NEXT: add 3, 3, 5
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; CHECK-P8-NEXT: extsh 3, 3
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; CHECK-P8-NEXT: blr
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; CHECK-NEXT: blr
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entry:
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%mul = mul i16 %b, %a
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%add = add i16 %mul, %c
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@ -58,18 +49,14 @@ entry:
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}
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define zeroext i32 @maddld32zeroext(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-P9-LABEL: maddld32zeroext:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-LABEL: maddld32zeroext:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P9-NEXT: clrldi 3, 3, 32
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: maddld32zeroext:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-P8-NEXT: clrldi 3, 3, 32
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; CHECK-P8-NEXT: blr
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, %a
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@ -77,18 +64,14 @@ entry:
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}
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define signext i32 @maddld32nsw(i32 signext %a, i32 signext %b) {
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; CHECK-P9-LABEL: maddld32nsw:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-LABEL: maddld32nsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P9-NEXT: extsw 3, 3
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: maddld32nsw:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-P8-NEXT: extsw 3, 3
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; CHECK-P8-NEXT: blr
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul nsw i32 %b, %a
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%add = add nsw i32 %mul, %a
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@ -96,20 +79,161 @@ entry:
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}
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define zeroext i32 @maddld32nuw(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-P9-LABEL: maddld32nuw:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-LABEL: maddld32nuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P9-NEXT: clrldi 3, 3, 32
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P8-LABEL: maddld32nuw:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-P8-NEXT: clrldi 3, 3, 32
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; CHECK-P8-NEXT: blr
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, %a
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%add = add nuw i32 %mul, %a
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ret i32 %add
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}
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define signext i64 @maddld64_imm(i64 signext %a, i64 signext %b) {
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; CHECK-LABEL: maddld64_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 4, 4, 13
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; CHECK-NEXT: add 3, 4, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i64 %b, 13
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%add = add i64 %mul, %a
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ret i64 %add
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}
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define signext i32 @maddld32_imm(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: maddld32_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, 13
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ret i32 %add
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}
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define signext i16 @maddld16_imm(i16 signext %a, i16 signext %b, i16 signext %c) {
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; CHECK-LABEL: maddld16_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 3, 4, 13
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; CHECK-NEXT: add 3, 3, 5
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; CHECK-NEXT: extsh 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i16 %b, 13
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%add = add i16 %mul, %c
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ret i16 %add
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}
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define zeroext i32 @maddld32zeroext_imm(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: maddld32zeroext_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, 13
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ret i32 %add
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}
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define signext i32 @maddld32nsw_imm(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: maddld32nsw_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 4, 4, 13
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; CHECK-NEXT: add 3, 4, 3
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul nsw i32 %b, 13
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_imm(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, %a
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%add = add nuw i32 %mul, 13
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_imm_imm(i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_imm_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 3, 3, 18
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, 18
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%add = add nuw i32 %mul, 13
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_bigimm_imm(i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_bigimm_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: lis 4, 26127
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; CHECK-NEXT: ori 4, 4, 63251
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; CHECK-NEXT: mullw 3, 3, 4
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, 1712322323
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%add = add nuw i32 %mul, 13
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_bigimm_bigimm(i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_bigimm_bigimm:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: lis 4, -865
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; CHECK-P9-NEXT: lis 5, 26127
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; CHECK-P9-NEXT: ori 4, 4, 42779
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; CHECK-P9-NEXT: ori 5, 5, 63251
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; CHECK-P9-NEXT: maddld 3, 3, 5, 4
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; CHECK-P8-NEXT: lis 4, 26127
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; CHECK-P8-NEXT: ori 4, 4, 63251
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; CHECK-P8-NEXT: mullw 3, 3, 4
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; CHECK-P8-NEXT: addi 3, 3, -22757
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; CHECK-P8-NEXT: addis 3, 3, -864
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, 1712322323
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%add = add nuw i32 %mul, 17123223323
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ret i32 %add
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}
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