forked from OSchip/llvm-project
Remove some register allocation order dependencies.
llvm-svn: 172874
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a4d8747d0f
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@ -14,12 +14,12 @@ entry:
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declare float @fabsf(float)
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declare float @fabsf(float)
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; VFP2: test:
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; VFP2: test:
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; VFP2: vabs.f32 s2, s2
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; VFP2: vabs.f32 s
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; NFP1: test:
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; NFP1: test:
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; NFP1: vabs.f32 d1, d1
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; NFP1: vabs.f32 d
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; NFP0: test:
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; NFP0: test:
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; NFP0: vabs.f32 s2, s2
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; NFP0: vabs.f32 s
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; CORTEXA8: test:
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; CORTEXA8: test:
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; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
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; CORTEXA8: vadd.f32 [[D1:d[0-9]+]]
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@ -10,14 +10,14 @@ entry:
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}
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}
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; VFP2: test:
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; VFP2: test:
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; VFP2: vdiv.f32 s0, s2, s0
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; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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; NFP1: test:
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; NFP1: test:
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; NFP1: vdiv.f32 s0, s2, s0
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; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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; NFP0: test:
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; NFP0: test:
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; NFP0: vdiv.f32 s0, s2, s0
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; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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; CORTEXA8: test:
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; CORTEXA8: test:
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; CORTEXA8: vdiv.f32 s0, s2, s0
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; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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; CORTEXA9: test:
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; CORTEXA9: test:
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; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
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@ -46,8 +46,8 @@ entry:
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; NEON: vnmla.f64
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; NEON: vnmla.f64
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; A8: t3:
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; A8: t3:
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; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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; A8: vnmul.f64 d
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; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d
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%0 = fmul double %a, %b
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%0 = fmul double %a, %b
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%1 = fsub double -0.0, %0
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%1 = fsub double -0.0, %0
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%2 = fsub double %1, %acc
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%2 = fsub double %1, %acc
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@ -63,8 +63,8 @@ entry:
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; NEON: vnmla.f64
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; NEON: vnmla.f64
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; A8: t4:
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; A8: t4:
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; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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; A8: vnmul.f64 d
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; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}}
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; A8: vsub.f64 d
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%0 = fmul double %a, %b
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%0 = fmul double %a, %b
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%1 = fmul double -1.0, %0
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%1 = fmul double -1.0, %0
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%2 = fsub double %1, %acc
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%2 = fsub double %1, %acc
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@ -7,7 +7,7 @@ define float @foo(float %a, float %b) {
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entry:
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entry:
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; CHECK: foo
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; CHECK: foo
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; CORTEXM3: blx ___mulsf3
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; CORTEXM3: blx ___mulsf3
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; CORTEXM4: vmul.f32 s0, s2, s0
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; CORTEXM4: vmul.f32 s
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; CORTEXA8: vmul.f32 d
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; CORTEXA8: vmul.f32 d
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%0 = fmul float %a, %b
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%0 = fmul float %a, %b
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ret float %0
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ret float %0
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