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[GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero 

Similar to `DAGCombiner::visitRotate`.

This makes `rotl_bitwidth_cst` in postlegalizercombiner-rotate.mir reduce down
to a COPY. Modify the checkline to make sure that only rotate_out_of_range
runs there.

Differential Revision: https://reviews.llvm.org/D109264
This commit is contained in:
Jessica Paquette 2021-09-03 17:55:13 -07:00
parent aca14c8cf1
commit ac4896e2f3
3 changed files with 39 additions and 2 deletions
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2
llvm/include/llvm/Target/GlobalISel/Combine.td
View File

@ -281,7 +281,7 @@ def select_constant_cmp: GICombineRule<
def right_identity_zero: GICombineRule<
(defs root:$root),
(match (wip_match_opcode G_SUB, G_ADD, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR,
G_PTR_ADD):$root,
G_PTR_ADD, G_ROTL, G_ROTR):$root,
[{ return Helper.matchConstantOp(${root}->getOperand(2), 0); }]),
(apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
>;

3
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-rotate.mir
View File

@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner --aarch64postlegalizercombinerhelper-only-enable-rule="rotate_out_of_range" -verify-machineinstrs %s -o - | FileCheck %s
# REQUIRES: asserts
# Check that we simplify the constant rotate amount to be in range.
---

36
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
View File

@ -325,3 +325,39 @@ body: |
%op:_(p0) = G_PTR_ADD %x(p0), %cst
$x0 = COPY %op(p0)
RET_ReallyLR implicit $x0
...
---
name: right_identity_rotl
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: right_identity_rotl
; CHECK: liveins: $w0, $w1
; CHECK: %copy:_(s32) = COPY $w0
; CHECK: $w0 = COPY %copy(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%zero:_(s32) = G_CONSTANT i32 0
%rot:_(s32) = G_ROTL %copy(s32), %zero(s32)
$w0 = COPY %rot(s32)
RET_ReallyLR implicit $w0
...
...
---
name: right_identity_rotr
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: right_identity_rotr
; CHECK: liveins: $w0, $w1
; CHECK: %copy:_(s32) = COPY $w0
; CHECK: $w0 = COPY %copy(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%zero:_(s32) = G_CONSTANT i32 0
%rot:_(s32) = G_ROTR %copy(s32), %zero(s32)
$w0 = COPY %rot(s32)
RET_ReallyLR implicit $w0
...