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[WebAssembly] Prototype `f32x4.relaxed_dot_bf16x8_add_f32` 

As proposed in https://github.com/WebAssembly/relaxed-simd/issues/77. Only an
LLVM intrinsic and a clang builtin are implemented. Since there is no bfloat16
type, use u16 to represent the bfloats in the builtin function arguments.

Differential Revision: https://reviews.llvm.org/D133428
This commit is contained in:
Thomas Lively 2022-09-08 08:07:48 -07:00
parent 5e96cea1db
commit ac3b8df8f2
6 changed files with 48 additions and 0 deletions
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1
clang/include/clang/Basic/BuiltinsWebAssembly.def
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@ -188,6 +188,7 @@ TARGET_BUILTIN(__builtin_wasm_relaxed_q15mulr_s_i16x8, "V8sV8sV8s", "nc", "relax
TARGET_BUILTIN(__builtin_wasm_dot_i8x16_i7x16_s_i16x8, "V8sV16ScV16Sc", "nc", "relaxed-simd")
TARGET_BUILTIN(__builtin_wasm_dot_i8x16_i7x16_add_s_i32x4, "V4iV16ScV16ScV4i", "nc", "relaxed-simd")
TARGET_BUILTIN(__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4, "V4fV8UsV8UsV4f", "nc", "relaxed-simd")
#undef BUILTIN
#undef TARGET_BUILTIN

8
clang/lib/CodeGen/CGBuiltin.cpp
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@ -18870,6 +18870,14 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
CGM.getIntrinsic(Intrinsic::wasm_dot_i8x16_i7x16_add_signed);
return Builder.CreateCall(Callee, {LHS, RHS, Acc});
}
case WebAssembly::BI__builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4: {
Value *LHS = EmitScalarExpr(E->getArg(0));
Value *RHS = EmitScalarExpr(E->getArg(1));
Value *Acc = EmitScalarExpr(E->getArg(2));
Function *Callee =
CGM.getIntrinsic(Intrinsic::wasm_relaxed_dot_bf16x8_add_f32);
return Builder.CreateCall(Callee, {LHS, RHS, Acc});
}
default:
return nullptr;
}

7
clang/test/CodeGen/builtins-wasm.c
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@ -794,3 +794,10 @@ i32x4 dot_i8x16_i7x16_add_s_i32x4(i8x16 a, i8x16 b, i32x4 c) {
// WEBASSEMBLY-SAME: <16 x i8> %a, <16 x i8> %b, <4 x i32> %c)
// WEBASSEMBLY-NEXT: ret
}
f32x4 relaxed_dot_bf16x8_add_f32_f32x4(u16x8 a, u16x8 b, f32x4 c) {
return __builtin_wasm_relaxed_dot_bf16x8_add_f32_f32x4(a, b, c);
// WEBASSEMBLY: call <4 x float> @llvm.wasm.relaxed.dot.bf16x8.add.f32
// WEBASSEMBLY-SAME: <8 x i16> %a, <8 x i16> %b, <4 x float> %c)
// WEBASSEMBLY-NEXT: ret
}

6
llvm/include/llvm/IR/IntrinsicsWebAssembly.td
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@ -285,6 +285,12 @@ def int_wasm_dot_i8x16_i7x16_add_signed:
[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v4i32_ty],
[IntrNoMem, IntrSpeculatable]>;
def int_wasm_relaxed_dot_bf16x8_add_f32:
Intrinsic<[llvm_v4f32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v4f32_ty],
[IntrNoMem, IntrSpeculatable]>;
//===----------------------------------------------------------------------===//
// Thread-local storage intrinsics
//===----------------------------------------------------------------------===//

12
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
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@ -1466,3 +1466,15 @@ defm RELAXED_DOT_ADD :
(v16i8 V128:$lhs), (v16i8 V128:$rhs), (v4i32 V128:$acc)))],
"i32x4.dot_i8x16_i7x16_add_s\t$dst, $lhs, $rhs, $acc",
"i32x4.dot_i8x16_i7x16_add_s", 0x113>;
//===----------------------------------------------------------------------===//
// Relaxed BFloat16 dot product
//===----------------------------------------------------------------------===//
defm RELAXED_DOT_BFLOAT :
RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, V128:$acc),
(outs), (ins),
[(set (v4f32 V128:$dst), (int_wasm_relaxed_dot_bf16x8_add_f32
(v8i16 V128:$lhs), (v8i16 V128:$rhs), (v4f32 V128:$acc)))],
"f32x4.relaxed_dot_bf16x8_add_f32\t$dst, $lhs, $rhs, $acc",
"f32x4.relaxed_dot_bf16x8_add_f32", 0x114>;

14
llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
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@ -786,6 +786,20 @@ define <4 x float> @relaxed_max_v4f32(<4 x float> %a, <4 x float> %b) {
ret <4 x float> %v
}
; CHECK-LABEL: relaxed_dot_bf16x8_add_f32:
; CHECK-NEXT: .functype relaxed_dot_bf16x8_add_f32 (v128, v128, v128) -> (v128){{$}}
; CHECK-NEXT: f32x4.relaxed_dot_bf16x8_add_f32 $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
declare <4 x float> @llvm.wasm.relaxed.dot.bf16x8.add.f32(<8 x i16>, <8 x i16>,
<4 x float>)
define <4 x float> @relaxed_dot_bf16x8_add_f32(<8 x i16> %a, <8 x i16> %b,
<4 x float> %c) {
%v = call <4 x float> @llvm.wasm.relaxed.dot.bf16x8.add.f32(
<8 x i16> %a, <8 x i16> %b, <4 x float> %c
)
ret <4 x float> %v
}
; ==============================================================================
; 2 x f64
; ==============================================================================