diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index c871cb3b7864..8ba501ecbcbe 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -255,7 +255,7 @@ const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { }; // 64-bit Darwin calling convention. static const unsigned Darwin64_CalleeSaveRegs[] = { - PPC::X13, PPC::X14, PPC::X15, + PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, @@ -306,7 +306,7 @@ PPCRegisterInfo::getCalleeSaveRegClasses() const { // 64-bit Darwin calling convention. static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = { - &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, + &PPC::G8RCRegClass,&PPC::G8RCRegClass, &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 7f5668800c1e..6c18e17eebbd 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -234,7 +234,7 @@ def GPRC : RegisterClass<"PPC", [i32], 32, def G8RC : RegisterClass<"PPC", [i64], 64, [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17, - X16, X15, X14, X13, X31, X0, X1, LR8]> + X16, X15, X14, X31, X13, X0, X1, LR8]> { let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; @@ -248,9 +248,9 @@ def G8RC : RegisterClass<"PPC", [i64], 64, G8RCClass::iterator G8RCClass::allocation_order_end(const MachineFunction &MF) const { if (needsFP(MF)) - return end()-4; + return end()-5; else - return end()-3; + return end()-4; } }]; }