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llvm-svn: 40132
This commit is contained in:
Evan Cheng 2007-07-21 00:34:19 +00:00
parent 147d9fa57d
commit ac1591be42
14 changed files with 48 additions and 57 deletions
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4
llvm/lib/Target/ARM/ARMInstrInfo.td
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@ -654,7 +654,7 @@ let isLoad = 1, isReturn = 1, isTerminator = 1 in
"ldm${p}${addr:submode} $addr, $dst1",
[]>;
let isCall = 1, noResults = 1,
let isCall = 1,
Defs = [R0, R1, R2, R3, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
def BL : AXI<(outs), (ins i32imm:$func, variable_ops),
@ -677,7 +677,7 @@ let isCall = 1, noResults = 1,
}
}
let isBranch = 1, isTerminator = 1, noResults = 1 in {
let isBranch = 1, isTerminator = 1 in {
// B is "predicable" since it can be xformed into a Bcc.
let isBarrier = 1 in {
let isPredicable = 1 in

6
llvm/lib/Target/ARM/ARMInstrThumb.td
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@ -190,7 +190,7 @@ let isLoad = 1, isReturn = 1, isTerminator = 1 in
def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
"pop $dst1", []>;
let isCall = 1, noResults = 1,
let isCall = 1,
Defs = [R0, R1, R2, R3, LR,
D0, D1, D2, D3, D4, D5, D6, D7] in {
def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
@ -209,7 +209,7 @@ let isCall = 1, noResults = 1,
[(ARMcall_nolink GPR:$func)]>;
}
let isBranch = 1, isTerminator = 1, noResults = 1 in {
let isBranch = 1, isTerminator = 1 in {
let isBarrier = 1 in {
let isPredicable = 1 in
def tB : TI<(outs), (ins brtarget:$target), "b $target",
@ -227,7 +227,7 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in {
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1, noResults = 1 in
let isBranch = 1, isTerminator = 1 in
def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
[/*(ARMbrcond bb:$target, imm:$cc)*/]>;

2
llvm/lib/Target/Alpha/AlphaInstrFormats.td
View File

@ -97,7 +97,7 @@ class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> patt
//3.3.2
def target : Operand<OtherVT> {}
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
: InstAlpha<opcode, asmstr, itin> {
let OutOperandList = (ops);

12
llvm/lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -369,17 +369,17 @@ def : Pat<(setune GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0)>;
let isReturn = 1, isTerminator = 1, noResults = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in {
let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in {
def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", s_jsr>; //Return from subroutine
def RETDAGp : MbrpForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", [(retflag)], s_jsr>; //Return from subroutine
}
let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1,
let isBranch = 1, isTerminator = 1, isBarrier = 1,
Ra = 31, disp = 0 in
def JMP : MbrpForm< 0x1A, 0x00, (ops GPRC:$RS), "jmp $$31,($RS),0",
[(brind GPRC:$RS)], s_jsr>; //Jump
let isCall = 1, noResults = 1, Ra = 26,
let isCall = 1, Ra = 26,
Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
F0, F1,
@ -387,7 +387,7 @@ let isCall = 1, noResults = 1, Ra = 26,
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", [], s_jsr>; //Branch to subroutine
}
let isCall = 1, noResults = 1, Ra = 26, Rb = 27, disp = 0,
let isCall = 1, Ra = 26, Rb = 27, disp = 0,
Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
F0, F1,
@ -396,7 +396,7 @@ let isCall = 1, noResults = 1, Ra = 26, Rb = 27, disp = 0,
def JSR : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0", s_jsr>; //Jump to subroutine
}
let isCall = 1, noResults = 1, Ra = 23, Rb = 27, disp = 0,
let isCall = 1, Ra = 23, Rb = 27, disp = 0,
Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0", s_jsr>; //Jump to div or rem
@ -786,7 +786,7 @@ class br_fcc<bits<6> opc, string asmstr>
: BFormN<opc, (ops u64imm:$opc, F8RC:$R, target:$dst),
!strconcat(asmstr, " $R,$dst"), s_fbr>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
let Ra = 31 in
def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)], s_ubr>;

8
llvm/lib/Target/IA64/IA64InstrInfo.td
View File

@ -539,7 +539,7 @@ def CADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR
def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
"sub $dst = $imm, $src2">, isA;
let isStore = 1, noResults = 1 in {
let isStore = 1 in {
def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
"st1 [$dstPtr] = $value">, isM;
def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
@ -687,7 +687,7 @@ def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
(GETFSIG (FCVTFXUTRUNC FP:$src))>;
let isTerminator = 1, isBranch = 1, noResults = 1 in {
let isTerminator = 1, isBranch = 1 in {
def BRL_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins i64imm:$dst),
"(p0) brl.cond.sptk $dst">, isB;
def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst),
@ -696,7 +696,7 @@ let isTerminator = 1, isBranch = 1, noResults = 1 in {
"($qp) br.cond.sptk $dst">, isB;
}
let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
let isCall = 1, /* isTerminator = 1, isBranch = 1, */
Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
// all calls clobber non-callee-saved registers, and for now, they are these:
Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
@ -733,7 +733,7 @@ let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
}
// Return branch:
let isTerminator = 1, isReturn = 1, noResults = 1 in
let isTerminator = 1, isReturn = 1 in
def RET : AForm_DAG<0x03, 0x0b, (outs), (ins),
"br.ret.sptk.many rp",
[(retflag)]>, isB; // return

8
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -208,7 +208,7 @@ class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
[(OpNode CPURegs:$dst, addr:$addr)]>;
// Conditional Branch
let isBranch = 1, noResults=1, isTerminator=1 in
let isBranch = 1, isTerminator=1 in
class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
FI< op,
(outs),
@ -234,7 +234,7 @@ class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))]>;
// Unconditional branch
let hasCtrlDep=1, noResults=1, isTerminator=1 in
let hasCtrlDep=1, isTerminator=1 in
class JumpFJ<bits<6> op, string instr_asm>:
FJ< op,
(outs),
@ -242,7 +242,7 @@ class JumpFJ<bits<6> op, string instr_asm>:
!strconcat(instr_asm, " $target"),
[(br bb:$target)]>;
let hasCtrlDep=1, noResults=1, isTerminator=1, rd=0 in
let hasCtrlDep=1, isTerminator=1, rd=0 in
class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
FR< op,
func,
@ -407,7 +407,7 @@ def NOOP : FJ<0, (outs), (ins), "nop", []>;
// Ret instruction - as mips does not have "ret" a
// jr $ra must be generated.
let isReturn=1, isTerminator=1, hasDelaySlot=1, noResults=1,
let isReturn=1, isTerminator=1, hasDelaySlot=1,
isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
{
def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),

8
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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@ -70,7 +70,7 @@ let Defs = [LR8] in
PPC970_Unit_BRU;
// Macho ABI Calls.
let isCall = 1, noResults = 1, PPC970_Unit = 7,
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the PPC64 non-callee saved registers.
Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
@ -89,7 +89,7 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7,
// ELF 64 ABI Calls = Macho ABI Calls
// Used to define BL8_ELF and BLA8_ELF
let isCall = 1, noResults = 1, PPC970_Unit = 7,
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the PPC64 non-callee saved registers.
Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
@ -438,7 +438,7 @@ def LDU : DSForm_1<58, 1, (outs G8RC:$rD), (ins ptr_rc:$ea_result, memrix:$addr
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
let isStore = 1, PPC970_Unit = 2 in {
// Truncating stores.
def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
@ -505,7 +505,7 @@ def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
let isStore = 1, PPC970_Unit = 2 in {
def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
"stdux $rS, $dst", LdStSTD,

4
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
View File

@ -160,14 +160,12 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD",
[(set VRRC:$rD, (v4i32 (undef)))]>;
let noResults = 1 in {
def DSS : DSS_Form<822, (outs), (ins u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
"dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
def DST : DSS_Form<342, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
"dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
def DSTST : DSS_Form<374, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
"dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
}
def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
"mfvcr $vD", LdStGeneral,
@ -203,7 +201,7 @@ def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src),
[(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
PPC970_Unit_LSU;
let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
let isStore = 1, PPC970_Unit = 2 in { // Stores.
def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
"stvebx $rS, $dst", LdStGeneral,
[(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;

13
llvm/lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -345,7 +345,7 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
[]>;
}
let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
let isReturn = 1 in
def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
"b${p:cc}lr ${p:reg}", BrB,
@ -359,8 +359,7 @@ let Defs = [LR] in
def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
PPC970_Unit_BRU;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
noResults = 1, PPC970_Unit = 7 in {
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
let isBarrier = 1 in {
def B : IForm<18, 0, 0, (outs), (ins target:$dst),
"b $dst", BrB,
@ -376,7 +375,7 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
}
// Macho ABI Calls.
let isCall = 1, noResults = 1, PPC970_Unit = 7,
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the non-callee saved registers...
Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
@ -397,7 +396,7 @@ let isCall = 1, noResults = 1, PPC970_Unit = 7,
}
// ELF ABI Calls.
let isCall = 1, noResults = 1, PPC970_Unit = 7,
let isCall = 1, PPC970_Unit = 7,
// All calls clobber the non-callee saved registers...
Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,
@ -542,7 +541,7 @@ def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
//
// Unindexed (r+i) Stores.
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
let isStore = 1, PPC970_Unit = 2 in {
def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
[(truncstorei8 GPRC:$rS, iaddr:$src)]>;
@ -599,7 +598,7 @@ def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
// Indexed (r+r) Stores.
//
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
let isStore = 1, PPC970_Unit = 2 in {
def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
"stbx $rS, $dst", LdStGeneral,
[(truncstorei8 GPRC:$rS, xaddr:$dst)]>,

6
llvm/lib/Target/Sparc/SparcInstrInfo.td
View File

@ -267,7 +267,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>;
}
@ -464,7 +464,6 @@ class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
let noResults = 1;
}
let isBarrier = 1 in
@ -486,7 +485,6 @@ class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
let noResults = 1;
}
// FIXME: the encoding for the JIT should look at the condition field.
@ -498,7 +496,7 @@ def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
let Uses = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1, noResults = 1,
hasDelaySlot = 1, isCall = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
def CALL : InstSP<(outs), (ins calltarget:$dst),

1
llvm/lib/Target/Target.td
View File

@ -192,7 +192,6 @@ class Instruction {
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit noResults = 0; // Does this instruction produce no results?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.

11
llvm/lib/Target/X86/X86InstrFPStack.td
View File

@ -137,13 +137,12 @@ def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
[(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
let noResults = 1 in {
def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
[(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
[(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
[(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
[(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
}
// FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>;

16
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -403,14 +403,14 @@ def TRUNC_32to16 : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR32:$src),
// Return instructions.
let isTerminator = 1, isReturn = 1, isBarrier = 1,
hasCtrlDep = 1, noResults = 1 in {
hasCtrlDep = 1 in {
def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret $amt",
[(X86retflag imm:$amt)]>;
}
// All branches are RawFrm, Void, Branch, and Terminators
let isBranch = 1, isTerminator = 1, noResults = 1 in
let isBranch = 1, isTerminator = 1 in
class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
I<opcode, RawFrm, (outs), ins, asm, pattern>;
@ -418,7 +418,7 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in
let isBranch = 1, isBarrier = 1 in
def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l} {*}$dst",
[(brind GR32:$dst)]>;
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l} {*}$dst",
@ -464,7 +464,7 @@ def JNO : IBr<0x81, (ins brtarget:$dst), "jno $dst",
//===----------------------------------------------------------------------===//
// Call Instructions...
//
let isCall = 1, noResults = 1 in
let isCall = 1 in
// All calls clobber the non-callee saved registers...
let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
@ -478,13 +478,13 @@ let isCall = 1, noResults = 1 in
}
// Tail call stuff.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
[]>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp {*}$dst # TAIL CALL",
[]>;
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
"jmp {*}$dst # TAIL CALL", []>;
@ -2506,7 +2506,7 @@ def DWARF_LOC : I<0, Pseudo, (outs),
// EH Pseudo Instructions
//
let isTerminator = 1, isReturn = 1, isBarrier = 1,
hasCtrlDep = 1, noResults = 1 in {
hasCtrlDep = 1 in {
def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
"ret #eh_return, addr: $addr",
[(X86ehret GR32:$addr)]>;

6
llvm/lib/Target/X86/X86InstrX86-64.td
View File

@ -117,7 +117,7 @@ def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins),
//===----------------------------------------------------------------------===//
// Call Instructions...
//
let isCall = 1, noResults = 1 in
let isCall = 1 in
// All calls clobber the non-callee saved registers...
let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
@ -133,7 +133,7 @@ let isCall = 1, noResults = 1 in
}
// Branches
let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q} {*}$dst",
[(brind GR64:$dst)]>;
def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q} {*}$dst",
@ -597,7 +597,6 @@ def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
// Temporary hack: there is no patterns associated with these instructions
// so we have to tell tblgen that these do not produce results.
let noResults = 1 in {
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
"shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
Imp<[CL],[]>, TB;
@ -612,7 +611,6 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
"shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
TB;
} // noResults
//===----------------------------------------------------------------------===//
// Logical Instructions...