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AMDGPU: Fix operand name for v_interp_* 

Other VOP instructions call the output vdst

llvm-svn: 288856
This commit is contained in:
Matt Arsenault 2016-12-06 22:29:43 +00:00
parent 5369775a84
commit ac066f354a
2 changed files with 17 additions and 17 deletions
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32
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -50,11 +50,11 @@ let Uses = [M0, EXEC] in {
multiclass V_INTERP_P1_F32_m : VINTRP_m <
0x00000000,
(outs VGPR_32:$dst),
(outs VGPR_32:$vdst),
(ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr),
"v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]",
[(set f32:$dst, (AMDGPUinterp_p1 f32:$i, (i32 imm:$attr_chan),
(i32 imm:$attr)))]
"v_interp_p1_f32 $vdst, $i, $attr_chan, $attr, [m0]",
[(set f32:$vdst, (AMDGPUinterp_p1 f32:$i, (i32 imm:$attr_chan),
(i32 imm:$attr)))]
>;
let OtherPredicates = [has32BankLDS] in {
@ -63,31 +63,31 @@ defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
} // End OtherPredicates = [has32BankLDS]
let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {
let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1 in {
defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1
} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
defm V_INTERP_P2_F32 : VINTRP_m <
0x00000001,
(outs VGPR_32:$dst),
(outs VGPR_32:$vdst),
(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
[(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, f32:$j, (i32 imm:$attr_chan),
(i32 imm:$attr)))]>;
"v_interp_p2_f32 $vdst, [$src0], $j, $attr_chan, $attr, [m0]",
[(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$j, (i32 imm:$attr_chan),
(i32 imm:$attr)))]>;
} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
} // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
defm V_INTERP_MOV_F32 : VINTRP_m <
0x00000002,
(outs VGPR_32:$dst),
(outs VGPR_32:$vdst),
(ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr),
"v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]",
[(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
(i32 imm:$attr)))]>;
"v_interp_mov_f32 $vdst, $src0, $attr_chan, $attr, [m0]",
[(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan),
(i32 imm:$attr)))]>;
} // End Uses = [M0, EXEC]

2
llvm/test/MC/Disassembler/AMDGPU/missing_op.txt
View File

@ -1,5 +1,5 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble < %s | FileCheck %s -check-prefix=VI
#TODO: this test will fail when we fix v_interp_p2_f32 signature, remove it then
#VI: v_interp_p2_f32 16, [/*Missing OP1*/], /*Missing OP2*/, /*Missing OP3*/, /*Missing OP4*/
#VI: v_interp_p2_f32 v7, [v7], 16, /*Missing OP3*/, /*Missing OP4*/
0xd4 0x41 0x1d 0xd4