maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86][SSE] Don't duplicate Lower256IntArith functionality in LowerShift. NFC. 

LowerShift was using the same code as Lower256IntArith to split 256-bit vectors into 2 x 128-bit vectors, so now we just call Lower256IntArith.

llvm-svn: 264403
This commit is contained in:
Simon Pilgrim 2016-03-25 14:17:54 +00:00
parent e16b8df605
commit ac04923b0f
1 changed files with 2 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -19897,26 +19897,8 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
}
// Decompose 256-bit shifts into smaller 128-bit shifts.
if (VT.is256BitVector()) {
unsigned NumElems = VT.getVectorNumElements();
MVT EltVT = VT.getVectorElementType();
MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
// Extract the two vectors
SDValue V1 = extract128BitVector(R, 0, DAG, dl);
SDValue V2 = extract128BitVector(R, NumElems / 2, DAG, dl);
// Recreate the shift amount vectors
SDValue Amt1 = extract128BitVector(Amt, 0, DAG, dl);
SDValue Amt2 = extract128BitVector(Amt, NumElems / 2, DAG, dl);
// Issue new vector shifts for the smaller types
V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
// Concatenate the result back
return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
}
if (VT.is256BitVector())
return Lower256IntArith(Op, DAG);
return SDValue();
}