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[Hexagon] Fix a bug in r308502: post-inc offset is always 0 

llvm-svn: 308510
This commit is contained in:
Krzysztof Parzyszek 2017-07-19 19:17:32 +00:00
parent 04f3910537
commit ac01994db9
2 changed files with 24 additions and 2 deletions
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4
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1715,8 +1715,8 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
if (!MIa.getOperand(OffsetPosA).isImm() ||
!MIb.getOperand(OffsetPosB).isImm())
return false;
int OffsetA = OffA.getImm();
int OffsetB = OffB.getImm();
int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
// This is a mem access with the same base register and known offsets from it.
// Reason about it.

22
llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir Normal file
View File

@ -0,0 +1,22 @@
# RUN: llc -march=hexagon -start-before hexagon-packetizer %s -o - | FileCheck %s
# Check that we don't packetize these two instructions together. It happened
# earlier because "offset" in the post-increment instruction was taken to be 8.
# CHECK: memw(r0+#0) = #-1
# CHECK: }
# CHECK: {
# CHECK: r1 = memw(r0++#8)
--- |
define void @fred(i32* %a) { ret void }
...
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
liveins: %r0
S4_storeiri_io %r0, 0, -1 :: (store 4 into %ir.a)
%r1, %r0 = L2_loadri_pi %r0, 8 :: (load 4 from %ir.a)