diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 370af950942b..b0101e6f2610 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1715,8 +1715,8 @@ bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
   if (!MIa.getOperand(OffsetPosA).isImm() ||
       !MIb.getOperand(OffsetPosB).isImm())
     return false;
-  int OffsetA = OffA.getImm();
-  int OffsetB = OffB.getImm();
+  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
+  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
 
   // This is a mem access with the same base register and known offsets from it.
   // Reason about it.
diff --git a/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir b/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir
new file mode 100644
index 000000000000..69337e92ddaf
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir
@@ -0,0 +1,22 @@
+# RUN: llc -march=hexagon -start-before hexagon-packetizer %s -o - | FileCheck %s
+
+# Check that we don't packetize these two instructions together. It happened
+# earlier because "offset" in the post-increment instruction was taken to be 8.
+
+# CHECK: memw(r0+#0) = #-1
+# CHECK: }
+# CHECK: {
+# CHECK: r1 = memw(r0++#8)
+
+--- |
+  define void @fred(i32* %a) { ret void }
+...
+---
+name: fred
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: %r0
+      S4_storeiri_io %r0, 0, -1 :: (store 4 into %ir.a)
+      %r1, %r0 = L2_loadri_pi %r0, 8 :: (load 4 from %ir.a)