diff --git a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp index 715be37d6cb0..ab71bc126ccd 100644 --- a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -380,8 +380,8 @@ public: case AMDGPU::RAT_WRITE_CACHELESS_32_eg: case AMDGPU::RAT_WRITE_CACHELESS_64_eg: case AMDGPU::RAT_WRITE_CACHELESS_128_eg: - case AMDGPU::RAT_STORE_DWORD32_cm: - case AMDGPU::RAT_STORE_DWORD64_cm: + case AMDGPU::RAT_STORE_DWORD32: + case AMDGPU::RAT_STORE_DWORD64: DEBUG(dbgs() << CfCount << ":"; MI->dump();); CfCount++; break; diff --git a/llvm/lib/Target/R600/R600Instructions.td b/llvm/lib/Target/R600/R600Instructions.td index 52205cc5c72c..a67276ce6ee9 100644 --- a/llvm/lib/Target/R600/R600Instructions.td +++ b/llvm/lib/Target/R600/R600Instructions.td @@ -255,12 +255,12 @@ def TEX_ARRAY_MSAA : PatLeaf< }] >; -class EG_CF_RAT cfinst, bits <6> ratinst, bits<4> mask, dag outs, - dag ins, string asm, list pattern> : +class EG_CF_RAT cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask, + dag outs, dag ins, string asm, list pattern> : InstR600ISA , CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF { - let rat_id = 0; + let rat_id = ratid; let rat_inst = ratinst; let rim = 0; // XXX: Have a separate instruction for non-indexed writes. @@ -1260,6 +1260,20 @@ let Predicates = [isR700] in { def COS_r700 : COS_Common<0x6F>; } +//===----------------------------------------------------------------------===// +// Evergreen / Cayman store instructions +//===----------------------------------------------------------------------===// + +let Predicates = [isEGorCayman] in { + +class CF_MEM_RAT_CACHELESS rat_inst, bits<4> rat_id, bits<4> mask, dag ins, + string name, list pattern> + : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, + "MEM_RAT_CACHELESS "#name, pattern>; + +} // End Predicates = [isEGorCayman] + + //===----------------------------------------------------------------------===// // Evergreen Only instructions //===----------------------------------------------------------------------===// @@ -1288,36 +1302,32 @@ def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; //===----------------------------------------------------------------------===// // Memory read/write instructions //===----------------------------------------------------------------------===// + let usesCustomInserter = 1 in { -class RAT_WRITE_CACHELESS_eg mask, string name, - list pattern> - : EG_CF_RAT <0x57, 0x2, mask, (outs), ins, name, pattern> { -} - -} // End usesCustomInserter = 1 - // 32-bit store -def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg < +def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), - 0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop", + "STORE_RAW $rw_gpr, $index_gpr, $eop", [(global_store i32:$rw_gpr, i32:$index_gpr)] >; // 64-bit store -def RAT_WRITE_CACHELESS_64_eg : RAT_WRITE_CACHELESS_eg < +def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), - 0x3, "RAT_WRITE_CACHELESS_64_eg $rw_gpr.XY, $index_gpr, $eop", + "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", [(global_store v2i32:$rw_gpr, i32:$index_gpr)] >; //128-bit store -def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg < +def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), - 0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop", + "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", [(global_store v4i32:$rw_gpr, i32:$index_gpr)] >; +} // End usesCustomInserter = 1 + class VTX_READ_eg buffer_id, dag outs, list pattern> : VTX_WORD0_eg, VTX_READ { @@ -1785,23 +1795,16 @@ def : Pat < def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>; - -class RAT_STORE_DWORD_cm mask, dag ins, list pat> : EG_CF_RAT < - 0x57, 0x14, mask, (outs), ins, - "EXPORT_RAT_INST_STORE_DWORD $rw_gpr, $index_gpr", pat -> { +class RAT_STORE_DWORD mask> : + CF_MEM_RAT_CACHELESS <0x14, 0, mask, + (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr), + "STORE_DWORD $rw_gpr, $index_gpr", + [(global_store vt:$rw_gpr, i32:$index_gpr)]> { let eop = 0; // This bit is not used on Cayman. } -def RAT_STORE_DWORD32_cm : RAT_STORE_DWORD_cm <0x1, - (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr), - [(global_store i32:$rw_gpr, i32:$index_gpr)] ->; - -def RAT_STORE_DWORD64_cm : RAT_STORE_DWORD_cm <0x3, - (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr), - [(global_store v2i32:$rw_gpr, i32:$index_gpr)] ->; +def RAT_STORE_DWORD32 : RAT_STORE_DWORD ; +def RAT_STORE_DWORD64 : RAT_STORE_DWORD ; class VTX_READ_cm buffer_id, dag outs, list pattern> : VTX_WORD0_cm, VTX_READ { diff --git a/llvm/test/CodeGen/R600/load.ll b/llvm/test/CodeGen/R600/load.ll index f478ef5f8922..22aed6ab4d09 100644 --- a/llvm/test/CodeGen/R600/load.ll +++ b/llvm/test/CodeGen/R600/load.ll @@ -104,8 +104,8 @@ entry: } ; R600-CHECK: @load_i64 -; R600-CHECK: RAT -; R600-CHECK: RAT +; R600-CHECK: MEM_RAT +; R600-CHECK: MEM_RAT ; SI-CHECK: @load_i64 ; SI-CHECK: BUFFER_LOAD_DWORDX2 @@ -117,8 +117,8 @@ entry: } ; R600-CHECK: @load_i64_sext -; R600-CHECK: RAT -; R600-CHECK: RAT +; R600-CHECK: MEM_RAT +; R600-CHECK: MEM_RAT ; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x ; R600-CHECK: 31 ; SI-CHECK: @load_i64_sext @@ -135,8 +135,8 @@ entry: } ; R600-CHECK: @load_i64_zext -; R600-CHECK: RAT -; R600-CHECK: RAT +; R600-CHECK: MEM_RAT +; R600-CHECK: MEM_RAT define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = load i32 addrspace(1)* %in diff --git a/llvm/test/CodeGen/R600/store.ll b/llvm/test/CodeGen/R600/store.ll index 506f0b0fb14e..5dc0a84bbe5d 100644 --- a/llvm/test/CodeGen/R600/store.ll +++ b/llvm/test/CodeGen/R600/store.ll @@ -4,9 +4,9 @@ ; floating-point store ; EG-CHECK: @store_f32 -; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 ; CM-CHECK: @store_f32 -; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} ; SI-CHECK: @store_f32 ; SI-CHECK: BUFFER_STORE_DWORD @@ -17,9 +17,9 @@ define void @store_f32(float addrspace(1)* %out, float %in) { ; vec2 floating-point stores ; EG-CHECK: @store_v2f32 -; EG-CHECK: RAT_WRITE_CACHELESS_64_eg +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW ; CM-CHECK: @store_v2f32 -; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK: @store_v2f32 ; SI-CHECK: BUFFER_STORE_DWORDX2 @@ -39,9 +39,9 @@ entry: ; be two 32-bit stores. ; EG-CHECK: @vecload2 -; EG-CHECK: RAT_WRITE_CACHELESS_64_eg +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW ; CM-CHECK: @vecload2 -; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK: @vecload2 ; SI-CHECK: BUFFER_STORE_DWORDX2 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { diff --git a/llvm/test/CodeGen/R600/store.r600.ll b/llvm/test/CodeGen/R600/store.r600.ll index 5ffb7f1809f8..00589a0c6c86 100644 --- a/llvm/test/CodeGen/R600/store.r600.ll +++ b/llvm/test/CodeGen/R600/store.r600.ll @@ -4,7 +4,7 @@ ; v4i32 store ; EG-CHECK: @store_v4i32 -; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %1 = load <4 x i32> addrspace(1) * %in @@ -14,7 +14,7 @@ define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* % ; v4f32 store ; EG-CHECK: @store_v4f32 -; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %1 = load <4 x float> addrspace(1) * %in store <4 x float> %1, <4 x float> addrspace(1)* %out diff --git a/llvm/test/CodeGen/R600/work-item-intrinsics.ll b/llvm/test/CodeGen/R600/work-item-intrinsics.ll index 7998983ab2f8..26ef304d1f52 100644 --- a/llvm/test/CodeGen/R600/work-item-intrinsics.ll +++ b/llvm/test/CodeGen/R600/work-item-intrinsics.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s ; R600-CHECK: @ngroups_x -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[0].X ; SI-CHECK: @ngroups_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 0 @@ -16,7 +16,7 @@ entry: } ; R600-CHECK: @ngroups_y -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[0].Y ; SI-CHECK: @ngroups_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 1 @@ -30,7 +30,7 @@ entry: } ; R600-CHECK: @ngroups_z -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[0].Z ; SI-CHECK: @ngroups_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 2 @@ -44,7 +44,7 @@ entry: } ; R600-CHECK: @global_size_x -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[0].W ; SI-CHECK: @global_size_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 3 @@ -58,7 +58,7 @@ entry: } ; R600-CHECK: @global_size_y -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[1].X ; SI-CHECK: @global_size_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 4 @@ -72,7 +72,7 @@ entry: } ; R600-CHECK: @global_size_z -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[1].Y ; SI-CHECK: @global_size_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 5 @@ -86,7 +86,7 @@ entry: } ; R600-CHECK: @local_size_x -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[1].Z ; SI-CHECK: @local_size_x ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 6 @@ -100,7 +100,7 @@ entry: } ; R600-CHECK: @local_size_y -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[1].W ; SI-CHECK: @local_size_y ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 7 @@ -114,7 +114,7 @@ entry: } ; R600-CHECK: @local_size_z -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]] +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] ; R600-CHECK: MOV * [[VAL]], KC0[2].X ; SI-CHECK: @local_size_z ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 8 diff --git a/llvm/test/CodeGen/R600/zero_extend.ll b/llvm/test/CodeGen/R600/zero_extend.ll index 413b84953450..e0b9c31ae306 100644 --- a/llvm/test/CodeGen/R600/zero_extend.ll +++ b/llvm/test/CodeGen/R600/zero_extend.ll @@ -2,8 +2,8 @@ ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK ; R600-CHECK: @test -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg -; R600-CHECK: RAT_WRITE_CACHELESS_32_eg +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW ; SI-CHECK: @test ; SI-CHECK: V_MOV_B32_e32 [[ZERO:VGPR[0-9]]], 0