forked from OSchip/llvm-project
AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
Added intrinsics for cvtsi2ss/d instructions. Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D10430 llvm-svn: 239694
This commit is contained in:
Igor Breger
parent
2ebb0c57fb
commit
abe4a79b75
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@ -2998,6 +2998,20 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_cvtusi642sd : GCCBuiltin<"__builtin_ia32_cvtusi642sd">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
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llvm_i64_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsi2ss32 : GCCBuiltin<"__builtin_ia32_cvtsi2ss32">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
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llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsi2ss64 : GCCBuiltin<"__builtin_ia32_cvtsi2ss64">,
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Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
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llvm_i64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsi2sd32 : GCCBuiltin<"__builtin_ia32_cvtsi2sd32">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
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llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_cvtsi2sd64 : GCCBuiltin<"__builtin_ia32_cvtsi2sd64">,
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Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
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llvm_i64_ty, llvm_i32_ty], [IntrNoMem]>;
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}
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// Pack ops.
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@ -18578,6 +18578,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
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case X86ISD::ADDS: return "X86ISD::ADDS";
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case X86ISD::SUBS: return "X86ISD::SUBS";
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case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
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case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
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}
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return nullptr;
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}
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@ -417,6 +417,10 @@ namespace llvm {
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COMPRESS,
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EXPAND,
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//Convert Unsigned/Integer to Scalar Floating-Point Value
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//with rounding mode
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SINT_TO_FP_RND,
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UINT_TO_FP_RND,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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@ -4205,15 +4205,32 @@ let hasSideEffects = 0 in {
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} // hasSideEffects = 0
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}
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multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
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X86VectorVTInfo DstVT, X86MemOperand x86memop, string asm> {
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def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
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(ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
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!strconcat(asm,"\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
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[(set DstVT.RC:$dst,
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(OpNode (DstVT.VT DstVT.RC:$src1),
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SrcRC:$src2,
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(i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
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}
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multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
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X86VectorVTInfo DstVT, X86MemOperand x86memop, string asm> {
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defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, x86memop, asm>,
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avx512_vcvtsi<opc, SrcRC, DstVT.FRC, x86memop, asm>, VEX_LIG;
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}
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let Predicates = [HasAVX512] in {
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defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
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XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
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XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
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defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
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XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
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XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
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defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
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v4f32x_info, i32mem, "cvtsi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
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v4f32x_info, i64mem, "cvtsi2ss{q}">, XS, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
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v2f64x_info, i32mem, "cvtsi2sd{l}">, XD, EVEX_CD8<32, CD8VT1>;
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defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
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v2f64x_info, i64mem, "cvtsi2sd{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
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(VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
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@ -4233,14 +4250,14 @@ def : Pat<(f64 (sint_to_fp GR32:$src)),
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def : Pat<(f64 (sint_to_fp GR64:$src)),
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(VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
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defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
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XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
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XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
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defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR32,
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v4f32x_info, i32mem, "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
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v4f32x_info, i64mem, "cvtusi2ss{q}">, XS, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
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XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
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XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
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XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
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v2f64x_info, i64mem, "cvtusi2sd{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
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def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
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(VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
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@ -350,6 +350,12 @@ def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 3>,
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SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
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def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
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SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
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def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
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def X86SuintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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//===----------------------------------------------------------------------===//
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@ -242,6 +242,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx2_psubus_b, INTR_TYPE_2OP, X86ISD::SUBUS, 0),
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X86_INTRINSIC_DATA(avx2_psubus_w, INTR_TYPE_2OP, X86ISD::SUBUS, 0),
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X86_INTRINSIC_DATA(avx2_vperm2i128, INTR_TYPE_3OP, X86ISD::VPERM2X128, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2sd32, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2sd64, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2ss32, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_cvtsi2ss64, INTR_TYPE_3OP, X86ISD::SINT_TO_FP_RND, 0),
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X86_INTRINSIC_DATA(avx512_exp2_pd, INTR_TYPE_1OP_MASK_RM, X86ISD::EXP2, 0),
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X86_INTRINSIC_DATA(avx512_exp2_ps, INTR_TYPE_1OP_MASK_RM, X86ISD::EXP2, 0),
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X86_INTRINSIC_DATA(avx512_mask_add_pd_128, INTR_TYPE_2OP_MASK, ISD::FADD, 0),
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@ -2807,3 +2807,43 @@ define <2 x double> @test_max_sd(<2 x double> %a0, <2 x double> %a1) {
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%res = call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>%a0, <2 x double> %a1, <2 x double> zeroinitializer, i8 -1, i32 4)
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ret <2 x double> %res
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}
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define <2 x double> @test_x86_avx512_cvtsi2sd32(<2 x double> %a, i32 %b) {
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; CHECK-LABEL: test_x86_avx512_cvtsi2sd32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsi2sdl %edi, {rz-sae}, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x double> @llvm.x86.avx512.cvtsi2sd32(<2 x double> %a, i32 %b, i32 3) ; <<<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.avx512.cvtsi2sd32(<2 x double>, i32, i32) nounwind readnone
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define <2 x double> @test_x86_avx512_cvtsi2sd64(<2 x double> %a, i64 %b) {
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; CHECK-LABEL: test_x86_avx512_cvtsi2sd64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsi2sdq %rdi, {rz-sae}, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x double> @llvm.x86.avx512.cvtsi2sd64(<2 x double> %a, i64 %b, i32 3) ; <<<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.avx512.cvtsi2sd64(<2 x double>, i64, i32) nounwind readnone
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define <4 x float> @test_x86_avx512_cvtsi2ss32(<4 x float> %a, i32 %b) {
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; CHECK-LABEL: test_x86_avx512_cvtsi2ss32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsi2ssl %edi, {rz-sae}, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x float> @llvm.x86.avx512.cvtsi2ss32(<4 x float> %a, i32 %b, i32 3) ; <<<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.cvtsi2ss32(<4 x float>, i32, i32) nounwind readnone
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define <4 x float> @test_x86_avx512_cvtsi2ss64(<4 x float> %a, i64 %b) {
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; CHECK-LABEL: test_x86_avx512_cvtsi2ss64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsi2ssq %rdi, {rz-sae}, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x float> @llvm.x86.avx512.cvtsi2ss64(<4 x float> %a, i64 %b, i32 3) ; <<<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.cvtsi2ss64(<4 x float>, i64, i32) nounwind readnone
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@ -8812,4 +8812,496 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
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// CHECK: encoding: [0x62,0xe2,0x1d,0x50,0x36,0xb2,0xfc,0xfd,0xff,0xff]
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vpermd -516(%rdx){1to16}, %zmm28, %zmm22
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// CHECK: vcvtsi2sdl %eax, %xmm10, %xmm7
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// CHECK: encoding: [0xc5,0xab,0x2a,0xf8]
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vcvtsi2sd %eax, %xmm10, %xmm7
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// CHECK: vcvtsi2sdl %ebp, %xmm10, %xmm7
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// CHECK: encoding: [0xc5,0xab,0x2a,0xfd]
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vcvtsi2sd %ebp, %xmm10, %xmm7
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// CHECK: vcvtsi2sdl %r13d, %xmm10, %xmm7
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// CHECK: encoding: [0xc4,0xc1,0x2b,0x2a,0xfd]
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vcvtsi2sd %r13d, %xmm10, %xmm7
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// CHECK: vcvtsi2sdl (%rcx), %xmm10, %xmm7
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// CHECK: encoding: [0xc5,0xab,0x2a,0x39]
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vcvtsi2sdl (%rcx), %xmm10, %xmm7
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// CHECK: vcvtsi2sdl 291(%rax,%r14,8), %xmm10, %xmm7
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// CHECK: encoding: [0xc4,0xa1,0x2b,0x2a,0xbc,0xf0,0x23,0x01,0x00,0x00]
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vcvtsi2sdl 291(%rax,%r14,8), %xmm10, %xmm7
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// CHECK: vcvtsi2sdl 508(%rdx), %xmm10, %xmm7
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// CHECK: encoding: [0xc5,0xab,0x2a,0xba,0xfc,0x01,0x00,0x00]
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vcvtsi2sdl 508(%rdx), %xmm10, %xmm7
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// CHECK: vcvtsi2sdl 512(%rdx), %xmm10, %xmm7
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// CHECK: encoding: [0xc5,0xab,0x2a,0xba,0x00,0x02,0x00,0x00]
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vcvtsi2sdl 512(%rdx), %xmm10, %xmm7
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// CHECK: vcvtsi2sdl -512(%rdx), %xmm10, %xmm7
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// CHECK: encoding: [0xc5,0xab,0x2a,0xba,0x00,0xfe,0xff,0xff]
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vcvtsi2sdl -512(%rdx), %xmm10, %xmm7
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// CHECK: vcvtsi2sdl -516(%rdx), %xmm10, %xmm7
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// CHECK: encoding: [0xc5,0xab,0x2a,0xba,0xfc,0xfd,0xff,0xff]
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vcvtsi2sdl -516(%rdx), %xmm10, %xmm7
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// CHECK: vcvtsi2sdq %rax, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x61,0x9f,0x08,0x2a,0xe8]
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vcvtsi2sd %rax, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %rax, {rn-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x61,0x9f,0x18,0x2a,0xe8]
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vcvtsi2sd %rax, {rn-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %rax, {ru-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x61,0x9f,0x58,0x2a,0xe8]
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vcvtsi2sd %rax, {ru-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %rax, {rd-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x61,0x9f,0x38,0x2a,0xe8]
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vcvtsi2sd %rax, {rd-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %rax, {rz-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x61,0x9f,0x78,0x2a,0xe8]
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vcvtsi2sd %rax, {rz-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %r8, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x41,0x9f,0x08,0x2a,0xe8]
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vcvtsi2sd %r8, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %r8, {rn-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x41,0x9f,0x18,0x2a,0xe8]
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vcvtsi2sd %r8, {rn-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %r8, {ru-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x41,0x9f,0x58,0x2a,0xe8]
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vcvtsi2sd %r8, {ru-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %r8, {rd-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x41,0x9f,0x38,0x2a,0xe8]
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vcvtsi2sd %r8, {rd-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq %r8, {rz-sae}, %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x41,0x9f,0x78,0x2a,0xe8]
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vcvtsi2sd %r8, {rz-sae}, %xmm12, %xmm29
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// CHECK: vcvtsi2sdq (%rcx), %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x61,0x9f,0x08,0x2a,0x29]
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vcvtsi2sdq (%rcx), %xmm12, %xmm29
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// CHECK: vcvtsi2sdq 291(%rax,%r14,8), %xmm12, %xmm29
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// CHECK: encoding: [0x62,0x21,0x9f,0x08,0x2a,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtsi2sdq 291(%rax,%r14,8), %xmm12, %xmm29
|
||||
|
||||
// CHECK: vcvtsi2sdq 1016(%rdx), %xmm12, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x9f,0x08,0x2a,0x6a,0x7f]
|
||||
vcvtsi2sdq 1016(%rdx), %xmm12, %xmm29
|
||||
|
||||
// CHECK: vcvtsi2sdq 1024(%rdx), %xmm12, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x9f,0x08,0x2a,0xaa,0x00,0x04,0x00,0x00]
|
||||
vcvtsi2sdq 1024(%rdx), %xmm12, %xmm29
|
||||
|
||||
// CHECK: vcvtsi2sdq -1024(%rdx), %xmm12, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x9f,0x08,0x2a,0x6a,0x80]
|
||||
vcvtsi2sdq -1024(%rdx), %xmm12, %xmm29
|
||||
|
||||
// CHECK: vcvtsi2sdq -1032(%rdx), %xmm12, %xmm29
|
||||
// CHECK: encoding: [0x62,0x61,0x9f,0x08,0x2a,0xaa,0xf8,0xfb,0xff,0xff]
|
||||
vcvtsi2sdq -1032(%rdx), %xmm12, %xmm29
|
||||
|
||||
// CHECK: vcvtsi2ssl %eax, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x2a,0x2a,0xf8]
|
||||
vcvtsi2ss %eax, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %eax, {rn-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x18,0x2a,0xf8]
|
||||
vcvtsi2ss %eax, {rn-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %eax, {ru-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x58,0x2a,0xf8]
|
||||
vcvtsi2ss %eax, {ru-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %eax, {rd-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x38,0x2a,0xf8]
|
||||
vcvtsi2ss %eax, {rd-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %eax, {rz-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x78,0x2a,0xf8]
|
||||
vcvtsi2ss %eax, {rz-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %ebp, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x2a,0x2a,0xfd]
|
||||
vcvtsi2ss %ebp, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %ebp, {rn-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x18,0x2a,0xfd]
|
||||
vcvtsi2ss %ebp, {rn-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %ebp, {ru-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x58,0x2a,0xfd]
|
||||
vcvtsi2ss %ebp, {ru-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %ebp, {rd-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x38,0x2a,0xfd]
|
||||
vcvtsi2ss %ebp, {rd-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %ebp, {rz-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x71,0x2e,0x78,0x2a,0xfd]
|
||||
vcvtsi2ss %ebp, {rz-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %r13d, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc4,0x41,0x2a,0x2a,0xfd]
|
||||
vcvtsi2ss %r13d, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %r13d, {rn-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x51,0x2e,0x18,0x2a,0xfd]
|
||||
vcvtsi2ss %r13d, {rn-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %r13d, {ru-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x51,0x2e,0x58,0x2a,0xfd]
|
||||
vcvtsi2ss %r13d, {ru-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %r13d, {rd-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x51,0x2e,0x38,0x2a,0xfd]
|
||||
vcvtsi2ss %r13d, {rd-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl %r13d, {rz-sae}, %xmm10, %xmm15
|
||||
// CHECK: encoding: [0x62,0x51,0x2e,0x78,0x2a,0xfd]
|
||||
vcvtsi2ss %r13d, {rz-sae}, %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl (%rcx), %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x2a,0x2a,0x39]
|
||||
vcvtsi2ssl (%rcx), %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl 291(%rax,%r14,8), %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc4,0x21,0x2a,0x2a,0xbc,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtsi2ssl 291(%rax,%r14,8), %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl 508(%rdx), %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x2a,0x2a,0xba,0xfc,0x01,0x00,0x00]
|
||||
vcvtsi2ssl 508(%rdx), %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl 512(%rdx), %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x2a,0x2a,0xba,0x00,0x02,0x00,0x00]
|
||||
vcvtsi2ssl 512(%rdx), %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl -512(%rdx), %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x2a,0x2a,0xba,0x00,0xfe,0xff,0xff]
|
||||
vcvtsi2ssl -512(%rdx), %xmm10, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2ssl -516(%rdx), %xmm10, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x2a,0x2a,0xba,0xfc,0xfd,0xff,0xff]
|
||||
vcvtsi2ssl -516(%rdx), %xmm10, %xmm15
|
||||
// CHECK: vcvtsi2ssq %rax, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x08,0x2a,0xc0]
|
||||
vcvtsi2ss %rax, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %rax, {rn-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x18,0x2a,0xc0]
|
||||
vcvtsi2ss %rax, {rn-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %rax, {ru-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x58,0x2a,0xc0]
|
||||
vcvtsi2ss %rax, {ru-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %rax, {rd-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x38,0x2a,0xc0]
|
||||
vcvtsi2ss %rax, {rd-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %rax, {rz-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x78,0x2a,0xc0]
|
||||
vcvtsi2ss %rax, {rz-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %r8, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xc1,0xae,0x08,0x2a,0xc0]
|
||||
vcvtsi2ss %r8, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %r8, {rn-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xc1,0xae,0x18,0x2a,0xc0]
|
||||
vcvtsi2ss %r8, {rn-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %r8, {ru-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xc1,0xae,0x58,0x2a,0xc0]
|
||||
vcvtsi2ss %r8, {ru-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %r8, {rd-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xc1,0xae,0x38,0x2a,0xc0]
|
||||
vcvtsi2ss %r8, {rd-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq %r8, {rz-sae}, %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xc1,0xae,0x78,0x2a,0xc0]
|
||||
vcvtsi2ss %r8, {rz-sae}, %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq (%rcx), %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x08,0x2a,0x01]
|
||||
vcvtsi2ssq (%rcx), %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq 291(%rax,%r14,8), %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xa1,0xae,0x08,0x2a,0x84,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtsi2ssq 291(%rax,%r14,8), %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq 1016(%rdx), %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x08,0x2a,0x42,0x7f]
|
||||
vcvtsi2ssq 1016(%rdx), %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq 1024(%rdx), %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x08,0x2a,0x82,0x00,0x04,0x00,0x00]
|
||||
vcvtsi2ssq 1024(%rdx), %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq -1024(%rdx), %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x08,0x2a,0x42,0x80]
|
||||
vcvtsi2ssq -1024(%rdx), %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtsi2ssq -1032(%rdx), %xmm10, %xmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0xae,0x08,0x2a,0x82,0xf8,0xfb,0xff,0xff]
|
||||
vcvtsi2ssq -1032(%rdx), %xmm10, %xmm16
|
||||
|
||||
// CHECK: vcvtusi2sdl %eax, %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x77,0x08,0x7b,0xd8]
|
||||
vcvtusi2sd %eax, %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl %ebp, %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x77,0x08,0x7b,0xdd]
|
||||
vcvtusi2sd %ebp, %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl %r13d, %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xc1,0x77,0x08,0x7b,0xdd]
|
||||
vcvtusi2sd %r13d, %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl (%rcx), %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x77,0x08,0x7b,0x19]
|
||||
vcvtusi2sdl (%rcx), %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl 291(%rax,%r14,8), %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xa1,0x77,0x08,0x7b,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtusi2sdl 291(%rax,%r14,8), %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl 508(%rdx), %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x77,0x08,0x7b,0x5a,0x7f]
|
||||
vcvtusi2sdl 508(%rdx), %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl 512(%rdx), %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x77,0x08,0x7b,0x9a,0x00,0x02,0x00,0x00]
|
||||
vcvtusi2sdl 512(%rdx), %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl -512(%rdx), %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x77,0x08,0x7b,0x5a,0x80]
|
||||
vcvtusi2sdl -512(%rdx), %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdl -516(%rdx), %xmm1, %xmm19
|
||||
// CHECK: encoding: [0x62,0xe1,0x77,0x08,0x7b,0x9a,0xfc,0xfd,0xff,0xff]
|
||||
vcvtusi2sdl -516(%rdx), %xmm1, %xmm19
|
||||
|
||||
// CHECK: vcvtusi2sdq %rax, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x00,0x7b,0xf0]
|
||||
vcvtusi2sd %rax, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %rax, {rn-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x10,0x7b,0xf0]
|
||||
vcvtusi2sd %rax, {rn-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %rax, {ru-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x50,0x7b,0xf0]
|
||||
vcvtusi2sd %rax, {ru-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %rax, {rd-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x30,0x7b,0xf0]
|
||||
vcvtusi2sd %rax, {rd-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %rax, {rz-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x70,0x7b,0xf0]
|
||||
vcvtusi2sd %rax, {rz-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %r8, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xaf,0x00,0x7b,0xf0]
|
||||
vcvtusi2sd %r8, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %r8, {rn-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xaf,0x10,0x7b,0xf0]
|
||||
vcvtusi2sd %r8, {rn-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %r8, {ru-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xaf,0x50,0x7b,0xf0]
|
||||
vcvtusi2sd %r8, {ru-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %r8, {rd-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xaf,0x30,0x7b,0xf0]
|
||||
vcvtusi2sd %r8, {rd-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq %r8, {rz-sae}, %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xaf,0x70,0x7b,0xf0]
|
||||
vcvtusi2sd %r8, {rz-sae}, %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq (%rcx), %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x00,0x7b,0x31]
|
||||
vcvtusi2sdq (%rcx), %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq 291(%rax,%r14,8), %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x31,0xaf,0x00,0x7b,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtusi2sdq 291(%rax,%r14,8), %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq 1016(%rdx), %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x00,0x7b,0x72,0x7f]
|
||||
vcvtusi2sdq 1016(%rdx), %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq 1024(%rdx), %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x00,0x7b,0xb2,0x00,0x04,0x00,0x00]
|
||||
vcvtusi2sdq 1024(%rdx), %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq -1024(%rdx), %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x00,0x7b,0x72,0x80]
|
||||
vcvtusi2sdq -1024(%rdx), %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2sdq -1032(%rdx), %xmm26, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xaf,0x00,0x7b,0xb2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtusi2sdq -1032(%rdx), %xmm26, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssl %eax, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x00,0x7b,0xe8]
|
||||
vcvtusi2ss %eax, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %eax, {rn-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x10,0x7b,0xe8]
|
||||
vcvtusi2ss %eax, {rn-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %eax, {ru-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x50,0x7b,0xe8]
|
||||
vcvtusi2ss %eax, {ru-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %eax, {rd-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x30,0x7b,0xe8]
|
||||
vcvtusi2ss %eax, {rd-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %eax, {rz-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x70,0x7b,0xe8]
|
||||
vcvtusi2ss %eax, {rz-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %ebp, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x00,0x7b,0xed]
|
||||
vcvtusi2ss %ebp, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %ebp, {rn-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x10,0x7b,0xed]
|
||||
vcvtusi2ss %ebp, {rn-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %ebp, {ru-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x50,0x7b,0xed]
|
||||
vcvtusi2ss %ebp, {ru-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %ebp, {rd-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x30,0x7b,0xed]
|
||||
vcvtusi2ss %ebp, {rd-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %ebp, {rz-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x70,0x7b,0xed]
|
||||
vcvtusi2ss %ebp, {rz-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %r13d, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xd1,0x2e,0x00,0x7b,0xed]
|
||||
vcvtusi2ss %r13d, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %r13d, {rn-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xd1,0x2e,0x10,0x7b,0xed]
|
||||
vcvtusi2ss %r13d, {rn-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %r13d, {ru-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xd1,0x2e,0x50,0x7b,0xed]
|
||||
vcvtusi2ss %r13d, {ru-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %r13d, {rd-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xd1,0x2e,0x30,0x7b,0xed]
|
||||
vcvtusi2ss %r13d, {rd-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl %r13d, {rz-sae}, %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xd1,0x2e,0x70,0x7b,0xed]
|
||||
vcvtusi2ss %r13d, {rz-sae}, %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl (%rcx), %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x00,0x7b,0x29]
|
||||
vcvtusi2ssl (%rcx), %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl 291(%rax,%r14,8), %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xb1,0x2e,0x00,0x7b,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtusi2ssl 291(%rax,%r14,8), %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl 508(%rdx), %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x00,0x7b,0x6a,0x7f]
|
||||
vcvtusi2ssl 508(%rdx), %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl 512(%rdx), %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x00,0x7b,0xaa,0x00,0x02,0x00,0x00]
|
||||
vcvtusi2ssl 512(%rdx), %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl -512(%rdx), %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x00,0x7b,0x6a,0x80]
|
||||
vcvtusi2ssl -512(%rdx), %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssl -516(%rdx), %xmm26, %xmm5
|
||||
// CHECK: encoding: [0x62,0xf1,0x2e,0x00,0x7b,0xaa,0xfc,0xfd,0xff,0xff]
|
||||
vcvtusi2ssl -516(%rdx), %xmm26, %xmm5
|
||||
|
||||
// CHECK: vcvtusi2ssq %rax, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x00,0x7b,0xf0]
|
||||
vcvtusi2ss %rax, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %rax, {rn-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x10,0x7b,0xf0]
|
||||
vcvtusi2ss %rax, {rn-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %rax, {ru-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x50,0x7b,0xf0]
|
||||
vcvtusi2ss %rax, {ru-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %rax, {rd-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x30,0x7b,0xf0]
|
||||
vcvtusi2ss %rax, {rd-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %rax, {rz-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x70,0x7b,0xf0]
|
||||
vcvtusi2ss %rax, {rz-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %r8, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xce,0x00,0x7b,0xf0]
|
||||
vcvtusi2ss %r8, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %r8, {rn-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xce,0x10,0x7b,0xf0]
|
||||
vcvtusi2ss %r8, {rn-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %r8, {ru-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xce,0x50,0x7b,0xf0]
|
||||
vcvtusi2ss %r8, {ru-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %r8, {rd-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xce,0x30,0x7b,0xf0]
|
||||
vcvtusi2ss %r8, {rd-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq %r8, {rz-sae}, %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x51,0xce,0x70,0x7b,0xf0]
|
||||
vcvtusi2ss %r8, {rz-sae}, %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq (%rcx), %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x00,0x7b,0x31]
|
||||
vcvtusi2ssq (%rcx), %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq 291(%rax,%r14,8), %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x31,0xce,0x00,0x7b,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||
vcvtusi2ssq 291(%rax,%r14,8), %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq 1016(%rdx), %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x00,0x7b,0x72,0x7f]
|
||||
vcvtusi2ssq 1016(%rdx), %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq 1024(%rdx), %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x00,0x7b,0xb2,0x00,0x04,0x00,0x00]
|
||||
vcvtusi2ssq 1024(%rdx), %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq -1024(%rdx), %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x00,0x7b,0x72,0x80]
|
||||
vcvtusi2ssq -1024(%rdx), %xmm22, %xmm14
|
||||
|
||||
// CHECK: vcvtusi2ssq -1032(%rdx), %xmm22, %xmm14
|
||||
// CHECK: encoding: [0x62,0x71,0xce,0x00,0x7b,0xb2,0xf8,0xfb,0xff,0xff]
|
||||
vcvtusi2ssq -1032(%rdx), %xmm22, %xmm14
|
||||
|
|
|
|||
Loading…
Reference in New Issue