forked from OSchip/llvm-project
AMDGPU/GlobalISel: Cleanup constant legality
llvm-svn: 327774
This commit is contained in:
Matt Arsenault
parent
685d1e8157
commit
abdc4f2dc7
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@ -66,18 +66,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const SISubtarget &ST,
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setAction({G_BITCAST, S32}, Legal);
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setAction({G_BITCAST, 1, V2S16}, Legal);
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({S32, S64});
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getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_CONSTANT})
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.legalFor({S1, S32, S64});
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// FIXME: i1 operands to intrinsics should always be legal, but other i1
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// values may not be legal. We need to figure out how to distinguish
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// between these two scenarios.
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setAction({G_CONSTANT, S1}, Legal);
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setAction({G_CONSTANT, S32}, Legal);
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setAction({G_CONSTANT, S64}, Legal);
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setAction({G_FCONSTANT, S32}, Legal);
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setAction({G_FCONSTANT, S64}, Legal);
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setAction({G_IMPLICIT_DEF, S32}, Legal);
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setAction({G_IMPLICIT_DEF, S64}, Legal);
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setAction({G_FADD, S32}, Legal);
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@ -1,94 +1,60 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
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--- |
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define void @test_constant_i32() {
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ret void
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}
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define void @test_constant_i64() {
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ret void
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}
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define void @test_fconstant_f32() {
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ret void
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}
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define void @test_fconstant_f64() {
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ret void
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}
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
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attributes #1 = { nounwind }
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...
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---
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name: test_constant_i32
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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; CHECK-LABEL: name: test_constant_i32
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C1]](s1), [[C1]](s1)
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%0(s32) = G_CONSTANT i32 5
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%1(s1) = G_CONSTANT i1 0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1;
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; CHECK: $vgpr0 = COPY [[C]](s32)
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%0:_(s32) = G_CONSTANT i32 5
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$vgpr0 = COPY %0
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...
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---
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name: test_constant_i64
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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; CHECK-LABEL: name: test_constant_i64
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C1]](s1), [[C1]](s1)
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%0(s32) = G_CONSTANT i32 5
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%1(s1) = G_CONSTANT i1 0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1;
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
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; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64)
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%0:_(s64) = G_CONSTANT i64 5
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$vgpr0_vgpr1 = COPY %0
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...
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---
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name: test_fconstant_f32
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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; CHECK-LABEL: name: test_fconstant_f32
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
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; CHECK: $vgpr0 = COPY [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.500000e+00
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; CHECK: $vgpr0 = COPY [[C1]](s32)
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%0(s32) = G_FCONSTANT float 1.0
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%0:_(s32) = G_FCONSTANT float 1.0
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$vgpr0 = COPY %0
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%1(s32) = G_FCONSTANT float 7.5
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$vgpr0 = COPY %1
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...
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---
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name: test_fconstant_f64
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0:
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; CHECK-LABEL: name: test_fconstant_f64
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
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; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 7.500000e+00
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; CHECK: $vgpr0_vgpr1 = COPY [[C1]](s64)
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%0(s64) = G_FCONSTANT double 1.0
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%0:_(s64) = G_FCONSTANT double 1.0
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$vgpr0_vgpr1 = COPY %0
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%1(s64) = G_FCONSTANT double 7.5
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_constant_1
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body: |
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bb.0:
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; CHECK-LABEL: name: test_constant_1
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; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
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; CHECK: S_ENDPGM implicit [[C]](s1)
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%1:_(s1) = G_CONSTANT i1 0
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S_ENDPGM implicit %1
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...
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