forked from OSchip/llvm-project
[PowerPC] Combine ADD to ADDZE
On the ppc64le platform, if ir has the following form, define i64 @addze1(i64 %x, i64 %z) local_unnamed_addr #0 { entry: %cmp = icmp ne i64 %z, CONSTANT (-32767 <= CONSTANT <= 32768) %conv1 = zext i1 %cmp to i64 %add = add nsw i64 %conv1, %x ret i64 %add } we can optimize it to the form below. when C == 0 --> addze X, (addic Z, -1)) / add X, (zext(setne Z, C))-- \ when -32768 <= -C <= 32767 && C != 0 --> addze X, (addic (addi Z, -C), -1) Patch By: HLJ2009 (Li Jia He) Differential Revision: https://reviews.llvm.org/D51403 Reviewed By: Nemanjai llvm-svn: 341634
This commit is contained in:
QingShan Zhang
parent
9e6845d8e1
commit
abbb894ff5
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@ -1055,6 +1055,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
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// We have target-specific dag combine patterns for the following nodes:
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::SHL);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRL);
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@ -12470,6 +12471,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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SDLoc dl(N);
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switch (N->getOpcode()) {
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default: break;
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case ISD::ADD:
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return combineADD(N, DCI);
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case ISD::SHL:
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return combineSHL(N, DCI);
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case ISD::SRA:
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@ -14176,6 +14179,100 @@ SDValue PPCTargetLowering::combineSRL(SDNode *N, DAGCombinerInfo &DCI) const {
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return SDValue();
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}
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// Transform (add X, (zext(setne Z, C))) -> (addze X, (addic (addi Z, -C), -1))
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// Transform (add X, (zext(sete Z, C))) -> (addze X, (subfic (addi Z, -C), 0))
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// When C is zero, the equation (addi Z, -C) can be simplified to Z
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// Requirement: -C in [-32768, 32767], X and Z are MVT::i64 types
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static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
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const PPCSubtarget &Subtarget) {
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if (!Subtarget.isPPC64())
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return SDValue();
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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auto isZextOfCompareWithConstant = [](SDValue Op) {
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if (Op.getOpcode() != ISD::ZERO_EXTEND || !Op.hasOneUse() ||
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Op.getValueType() != MVT::i64)
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return false;
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SDValue Cmp = Op.getOperand(0);
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if (Cmp.getOpcode() != ISD::SETCC || !Cmp.hasOneUse() ||
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Cmp.getOperand(0).getValueType() != MVT::i64)
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return false;
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if (auto *Constant = dyn_cast<ConstantSDNode>(Cmp.getOperand(1))) {
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int64_t NegConstant = 0 - Constant->getSExtValue();
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// Due to the limitations of the addi instruction,
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// -C is required to be [-32768, 32767].
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return isInt<16>(NegConstant);
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}
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return false;
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};
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bool LHSHasPattern = isZextOfCompareWithConstant(LHS);
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bool RHSHasPattern = isZextOfCompareWithConstant(RHS);
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// If there is a pattern, canonicalize a zext operand to the RHS.
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if (LHSHasPattern && !RHSHasPattern)
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std::swap(LHS, RHS);
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else if (!LHSHasPattern && !RHSHasPattern)
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return SDValue();
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SDLoc DL(N);
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SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64);
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SDValue Cmp = RHS.getOperand(0);
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SDValue Z = Cmp.getOperand(0);
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auto *Constant = dyn_cast<ConstantSDNode>(Cmp.getOperand(1));
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assert(Constant && "Constant Should not be a null pointer.");
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int64_t NegConstant = 0 - Constant->getSExtValue();
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switch(cast<CondCodeSDNode>(Cmp.getOperand(2))->get()) {
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default: break;
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case ISD::SETNE: {
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// when C == 0
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// --> addze X, (addic Z, -1).carry
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// /
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// add X, (zext(setne Z, C))--
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// \ when -32768 <= -C <= 32767 && C != 0
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// --> addze X, (addic (addi Z, -C), -1).carry
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SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
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DAG.getConstant(NegConstant, DL, MVT::i64));
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SDValue AddOrZ = NegConstant != 0 ? Add : Z;
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SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
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AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64));
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return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
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SDValue(Addc.getNode(), 1));
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}
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case ISD::SETEQ: {
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// when C == 0
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// --> addze X, (subfic Z, 0).carry
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// /
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// add X, (zext(sete Z, C))--
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// \ when -32768 <= -C <= 32767 && C != 0
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// --> addze X, (subfic (addi Z, -C), 0).carry
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SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
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DAG.getConstant(NegConstant, DL, MVT::i64));
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SDValue AddOrZ = NegConstant != 0 ? Add : Z;
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SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
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DAG.getConstant(0, DL, MVT::i64), AddOrZ);
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return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
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SDValue(Subc.getNode(), 1));
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}
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}
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return SDValue();
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}
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SDValue PPCTargetLowering::combineADD(SDNode *N, DAGCombinerInfo &DCI) const {
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if (auto Value = combineADDToADDZE(N, DCI.DAG, Subtarget))
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return Value;
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return SDValue();
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}
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bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
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// Only duplicate to increase tail-calls for the 64bit SysV ABIs.
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if (!Subtarget.isSVR4ABI() || !Subtarget.isPPC64())
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@ -1092,6 +1092,7 @@ namespace llvm {
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SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
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/// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
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/// SETCC with integer subtraction when (1) there is a legal way of doing it
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@ -0,0 +1,172 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s
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define i64 @addze1(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addic [[REG1:r[0-9]+]], [[REG1]], -1
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, 0
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze2(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subfic [[REG1:r[0-9]+]], [[REG1]], 0
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, 0
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze3(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768
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; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, 32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze4(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768
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; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, 32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze5(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767
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; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, -32767
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze6(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767
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; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, -32767
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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; element is out of range
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define i64 @test1(i64 %X, i64 %Z) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
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; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, -32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test2(i64 %X, i64 %Z) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
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; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, -32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test3(i64 %X, i64 %Z) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], 0
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; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
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; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, 32769
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test4(i64 %X, i64 %Z) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], 0
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; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
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; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, 32769
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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; comparison of two registers
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define i64 @test5(i64 %X, i64 %Y, i64 %Z) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
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; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
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; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Y, %Z
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test6(i64 %X, i64 %Y, i64 %Z) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
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; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
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; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Y, %Z
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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