forked from OSchip/llvm-project
Revert "[LoopVectorize][AArch64] Enable ordered reductions by default for AArch64"
This reverts commit f4122398e7
to
investigate a crash exposed by it.
The patch breaks building the code below with `clang -O2 --target=aarch64-linux`
int a;
double b, c;
void d() {
for (; a; a++) {
b += c;
c = a;
}
}
This commit is contained in:
parent
5ca7131eb3
commit
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@ -662,9 +662,6 @@ public:
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/// Return true if the target supports masked expand load.
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bool isLegalMaskedExpandLoad(Type *DataType) const;
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/// Return true if we should be enabling ordered reductions for the target.
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bool enableOrderedReductions() const;
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/// Return true if the target has a unified operation to calculate division
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/// and remainder. If so, the additional implicit multiplication and
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/// subtraction required to calculate a remainder from division are free. This
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@ -1511,7 +1508,6 @@ public:
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virtual bool isLegalMaskedGather(Type *DataType, Align Alignment) = 0;
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virtual bool isLegalMaskedCompressStore(Type *DataType) = 0;
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virtual bool isLegalMaskedExpandLoad(Type *DataType) = 0;
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virtual bool enableOrderedReductions() = 0;
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virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0;
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virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
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virtual bool prefersVectorizedAddressing() = 0;
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@ -1894,9 +1890,6 @@ public:
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bool isLegalMaskedExpandLoad(Type *DataType) override {
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return Impl.isLegalMaskedExpandLoad(DataType);
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}
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bool enableOrderedReductions() override {
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return Impl.enableOrderedReductions();
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}
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bool hasDivRemOp(Type *DataType, bool IsSigned) override {
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return Impl.hasDivRemOp(DataType, IsSigned);
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}
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@ -263,8 +263,6 @@ public:
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bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
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bool enableOrderedReductions() const { return false; }
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bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
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bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
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@ -410,10 +410,6 @@ bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
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return TTIImpl->isLegalMaskedExpandLoad(DataType);
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}
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bool TargetTransformInfo::enableOrderedReductions() const {
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return TTIImpl->enableOrderedReductions();
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}
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bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
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return TTIImpl->hasDivRemOp(DataType, IsSigned);
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}
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@ -299,8 +299,6 @@ public:
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return BaseT::isLegalNTStore(DataType, Alignment);
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}
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bool enableOrderedReductions() const { return true; }
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InstructionCost getInterleavedMemoryOpCost(
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unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
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Align Alignment, unsigned AddressSpace,
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@ -331,7 +331,7 @@ static cl::opt<bool>
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cl::desc("Prefer in-loop vector reductions, "
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"overriding the targets preference."));
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static cl::opt<bool> ForceOrderedReductions(
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cl::opt<bool> ForceOrderedReductions(
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"force-ordered-reductions", cl::init(false), cl::Hidden,
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cl::desc("Enable the vectorisation of loops with in-order (strict) "
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"FP reductions"));
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@ -1317,7 +1317,8 @@ public:
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/// the IsOrdered flag of RdxDesc is set and we do not allow reordering
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/// of FP operations.
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bool useOrderedReductions(const RecurrenceDescriptor &RdxDesc) {
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return !Hints->allowReordering() && RdxDesc.isOrdered();
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return ForceOrderedReductions && !Hints->allowReordering() &&
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RdxDesc.isOrdered();
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}
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/// \returns The smallest bitwidth each instruction can be represented with.
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@ -10224,13 +10225,7 @@ bool LoopVectorizePass::processLoop(Loop *L) {
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return false;
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}
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bool AllowOrderedReductions;
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// If the flag is set, use that instead and override the TTI behaviour.
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if (ForceOrderedReductions.getNumOccurrences() > 0)
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AllowOrderedReductions = ForceOrderedReductions;
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else
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AllowOrderedReductions = TTI->enableOrderedReductions();
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if (!LVL.canVectorizeFPMath(AllowOrderedReductions)) {
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if (!LVL.canVectorizeFPMath(ForceOrderedReductions)) {
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ORE->emit([&]() {
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auto *ExactFPMathInst = Requirements.getExactFPInst();
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return OptimizationRemarkAnalysisFPCommute(DEBUG_TYPE, "CantReorderFPOps",
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@ -2,7 +2,7 @@
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; RUN: opt < %s -loop-vectorize -scalable-vectorization=on -mtriple aarch64-unknown-linux-gnu -mattr=+sve -force-ordered-reductions=false -hints-allow-reordering=true -S 2>%t | FileCheck %s --check-prefix=CHECK-UNORDERED
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; RUN: opt < %s -loop-vectorize -scalable-vectorization=on -mtriple aarch64-unknown-linux-gnu -mattr=+sve -force-ordered-reductions=true -hints-allow-reordering=false -S 2>%t | FileCheck %s --check-prefix=CHECK-ORDERED
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; RUN: opt < %s -loop-vectorize -scalable-vectorization=on -mtriple aarch64-unknown-linux-gnu -mattr=+sve -force-ordered-reductions=true -hints-allow-reordering=true -S 2>%t | FileCheck %s --check-prefix=CHECK-UNORDERED
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; RUN: opt < %s -loop-vectorize -scalable-vectorization=on -mtriple aarch64-unknown-linux-gnu -mattr=+sve -hints-allow-reordering=false -S 2>%t | FileCheck %s --check-prefix=CHECK-ORDERED
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; RUN: opt < %s -loop-vectorize -scalable-vectorization=on -mtriple aarch64-unknown-linux-gnu -mattr=+sve -hints-allow-reordering=false -S 2>%t | FileCheck %s --check-prefix=CHECK-NOT-VECTORIZED
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define float @fadd_strict(float* noalias nocapture readonly %a, i64 %n) #0 {
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; CHECK-ORDERED-LABEL: @fadd_strict
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@ -2,7 +2,7 @@
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; RUN: opt < %s -loop-vectorize -mtriple aarch64-unknown-linux-gnu -force-ordered-reductions=false -hints-allow-reordering=true -S 2>%t | FileCheck %s --check-prefix=CHECK-UNORDERED
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; RUN: opt < %s -loop-vectorize -mtriple aarch64-unknown-linux-gnu -force-ordered-reductions=true -hints-allow-reordering=false -S 2>%t | FileCheck %s --check-prefix=CHECK-ORDERED
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; RUN: opt < %s -loop-vectorize -mtriple aarch64-unknown-linux-gnu -force-ordered-reductions=true -hints-allow-reordering=true -S 2>%t | FileCheck %s --check-prefix=CHECK-UNORDERED
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; RUN: opt < %s -loop-vectorize -mtriple aarch64-unknown-linux-gnu -hints-allow-reordering=false -S 2>%t | FileCheck %s --check-prefix=CHECK-ORDERED
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; RUN: opt < %s -loop-vectorize -mtriple aarch64-unknown-linux-gnu -hints-allow-reordering=false -S 2>%t | FileCheck %s --check-prefix=CHECK-NOT-VECTORIZED
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define float @fadd_strict(float* noalias nocapture readonly %a, i64 %n) {
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; CHECK-ORDERED-LABEL: @fadd_strict
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