forked from OSchip/llvm-project
[RISCV] Match vwmulsu_vx with scalar splat input.
This is a more generic version of D119110 that uses MaskedValueIsZero to do the matching and SimplifyDemandedBits to remove any unneeded AND instructions. Tests were taken from D119110. Reviewed By: Chenbing.Zheng Differential Revision: https://reviews.llvm.org/D119622
This commit is contained in:
Craig Topper
parent
d132b47bb9
commit
ab6e02dded
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@ -7786,12 +7786,15 @@ static SDValue combineMUL_VLToVWMUL_VL(SDNode *N, SelectionDAG &DAG,
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if (ScalarBits < EltBits)
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return SDValue();
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if (IsSignExt) {
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if (DAG.ComputeNumSignBits(Op1) <= (ScalarBits - NarrowSize))
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return SDValue();
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// If the LHS is a sign extend, try to use vwmul.
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if (IsSignExt && DAG.ComputeNumSignBits(Op1) > (ScalarBits - NarrowSize)) {
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// Can use vwmul.
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} else {
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// Otherwise try to use vwmulu or vwmulsu.
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APInt Mask = APInt::getBitsSetFrom(ScalarBits, NarrowSize);
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if (!DAG.MaskedValueIsZero(Op1, Mask))
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if (DAG.MaskedValueIsZero(Op1, Mask))
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IsVWMULSU = IsSignExt;
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else
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return SDValue();
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}
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@ -8438,6 +8441,16 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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return Gather;
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break;
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}
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case RISCVISD::VMV_V_X_VL: {
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// VMV.V.X only demands the vector element bitwidth from the scalar input.
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unsigned ScalarSize = N->getOperand(0).getValueSizeInBits();
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unsigned EltWidth = N->getValueType(0).getScalarSizeInBits();
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if (ScalarSize > EltWidth)
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if (SimplifyDemandedLowBitsHelper(0, EltWidth))
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return SDValue(N, 0);
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break;
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}
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}
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return SDValue();
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@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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define <2 x i16> @vwmulsu_v2i16(<2 x i8>* %x, <2 x i8>* %y) {
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; CHECK-LABEL: vwmulsu_v2i16:
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@ -681,3 +681,247 @@ define <16 x i64> @vwmulsu_vx_v16i64(<16 x i32>* %x, i32 %y) {
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%f = mul <16 x i64> %d, %e
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ret <16 x i64> %f
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}
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define <8 x i16> @vwmulsu_vx_v8i16_i8(<8 x i8>* %x, i8* %y) {
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; CHECK-LABEL: vwmulsu_vx_v8i16_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vle8.v v9, (a0)
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; CHECK-NEXT: lbu a0, 0(a1)
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; CHECK-NEXT: vwmulsu.vx v8, v9, a0
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; CHECK-NEXT: ret
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%a = load <8 x i8>, <8 x i8>* %x
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%b = load i8, i8* %y
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%c = zext i8 %b to i16
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%d = insertelement <8 x i16> poison, i16 %c, i32 0
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%e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer
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%f = sext <8 x i8> %a to <8 x i16>
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%g = mul <8 x i16> %e, %f
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ret <8 x i16> %g
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}
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define <8 x i16> @vwmulsu_vx_v8i16_i8_swap(<8 x i8>* %x, i8* %y) {
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; CHECK-LABEL: vwmulsu_vx_v8i16_i8_swap:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: lb a0, 0(a1)
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
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; CHECK-NEXT: vzext.vf2 v9, v8
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; CHECK-NEXT: vmul.vx v8, v9, a0
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; CHECK-NEXT: ret
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%a = load <8 x i8>, <8 x i8>* %x
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%b = load i8, i8* %y
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%c = sext i8 %b to i16
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%d = insertelement <8 x i16> poison, i16 %c, i32 0
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%e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer
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%f = zext <8 x i8> %a to <8 x i16>
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%g = mul <8 x i16> %e, %f
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ret <8 x i16> %g
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}
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define <4 x i32> @vwmulsu_vx_v4i32_i8(<4 x i16>* %x, i8* %y) {
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; CHECK-LABEL: vwmulsu_vx_v4i32_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
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; CHECK-NEXT: vle16.v v9, (a0)
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; CHECK-NEXT: lbu a0, 0(a1)
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; CHECK-NEXT: vwmul.vx v8, v9, a0
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; CHECK-NEXT: ret
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%a = load <4 x i16>, <4 x i16>* %x
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%b = load i8, i8* %y
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%c = zext i8 %b to i32
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%d = insertelement <4 x i32> poison, i32 %c, i32 0
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%e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer
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%f = sext <4 x i16> %a to <4 x i32>
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%g = mul <4 x i32> %e, %f
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ret <4 x i32> %g
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}
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define <4 x i32> @vwmulsu_vx_v4i32_i16(<4 x i16>* %x, i16* %y) {
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; CHECK-LABEL: vwmulsu_vx_v4i32_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
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; CHECK-NEXT: vle16.v v9, (a0)
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; CHECK-NEXT: lhu a0, 0(a1)
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; CHECK-NEXT: vwmulsu.vx v8, v9, a0
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; CHECK-NEXT: ret
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%a = load <4 x i16>, <4 x i16>* %x
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%b = load i16, i16* %y
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%c = zext i16 %b to i32
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%d = insertelement <4 x i32> poison, i32 %c, i32 0
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%e = shufflevector <4 x i32> %d, <4 x i32> poison, <4 x i32> zeroinitializer
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%f = sext <4 x i16> %a to <4 x i32>
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%g = mul <4 x i32> %e, %f
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ret <4 x i32> %g
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}
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define <2 x i64> @vwmulsu_vx_v2i64_i8(<2 x i32>* %x, i8* %y) {
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; RV32-LABEL: vwmulsu_vx_v2i64_i8:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV32-NEXT: lbu a1, 0(a1)
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; RV32-NEXT: vle32.v v8, (a0)
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; RV32-NEXT: sw zero, 12(sp)
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; RV32-NEXT: sw a1, 8(sp)
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; RV32-NEXT: addi a0, sp, 8
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; RV32-NEXT: vlse64.v v9, (a0), zero
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; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
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; RV32-NEXT: vsext.vf2 v10, v8
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; RV32-NEXT: vmul.vv v8, v9, v10
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vwmulsu_vx_v2i64_i8:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV64-NEXT: vle32.v v9, (a0)
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; RV64-NEXT: lbu a0, 0(a1)
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; RV64-NEXT: vwmul.vx v8, v9, a0
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; RV64-NEXT: ret
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%a = load <2 x i32>, <2 x i32>* %x
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%b = load i8, i8* %y
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%c = zext i8 %b to i64
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%d = insertelement <2 x i64> poison, i64 %c, i64 0
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%e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer
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%f = sext <2 x i32> %a to <2 x i64>
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%g = mul <2 x i64> %e, %f
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ret <2 x i64> %g
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}
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define <2 x i64> @vwmulsu_vx_v2i64_i16(<2 x i32>* %x, i16* %y) {
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; RV32-LABEL: vwmulsu_vx_v2i64_i16:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV32-NEXT: lhu a1, 0(a1)
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; RV32-NEXT: vle32.v v8, (a0)
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; RV32-NEXT: sw zero, 12(sp)
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; RV32-NEXT: sw a1, 8(sp)
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; RV32-NEXT: addi a0, sp, 8
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; RV32-NEXT: vlse64.v v9, (a0), zero
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; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
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; RV32-NEXT: vsext.vf2 v10, v8
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; RV32-NEXT: vmul.vv v8, v9, v10
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vwmulsu_vx_v2i64_i16:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV64-NEXT: vle32.v v9, (a0)
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; RV64-NEXT: lhu a0, 0(a1)
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; RV64-NEXT: vwmul.vx v8, v9, a0
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; RV64-NEXT: ret
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%a = load <2 x i32>, <2 x i32>* %x
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%b = load i16, i16* %y
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%c = zext i16 %b to i64
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%d = insertelement <2 x i64> poison, i64 %c, i64 0
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%e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer
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%f = sext <2 x i32> %a to <2 x i64>
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%g = mul <2 x i64> %e, %f
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ret <2 x i64> %g
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}
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define <2 x i64> @vwmulsu_vx_v2i64_i32(<2 x i32>* %x, i32* %y) {
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; RV32-LABEL: vwmulsu_vx_v2i64_i32:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV32-NEXT: lw a1, 0(a1)
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; RV32-NEXT: vle32.v v8, (a0)
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; RV32-NEXT: sw zero, 12(sp)
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; RV32-NEXT: sw a1, 8(sp)
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; RV32-NEXT: addi a0, sp, 8
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; RV32-NEXT: vlse64.v v9, (a0), zero
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; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, mu
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; RV32-NEXT: vsext.vf2 v10, v8
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; RV32-NEXT: vmul.vv v8, v9, v10
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vwmulsu_vx_v2i64_i32:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV64-NEXT: vle32.v v9, (a0)
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; RV64-NEXT: lwu a0, 0(a1)
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; RV64-NEXT: vwmulsu.vx v8, v9, a0
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; RV64-NEXT: ret
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%a = load <2 x i32>, <2 x i32>* %x
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%b = load i32, i32* %y
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%c = zext i32 %b to i64
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%d = insertelement <2 x i64> poison, i64 %c, i64 0
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%e = shufflevector <2 x i64> %d, <2 x i64> poison, <2 x i32> zeroinitializer
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%f = sext <2 x i32> %a to <2 x i64>
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%g = mul <2 x i64> %e, %f
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ret <2 x i64> %g
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}
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define <8 x i16> @vwmulsu_vx_v8i16_i8_and(<8 x i8>* %x, i16 %y) {
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; CHECK-LABEL: vwmulsu_vx_v8i16_i8_and:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vle8.v v9, (a0)
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; CHECK-NEXT: vwmulsu.vx v8, v9, a1
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; CHECK-NEXT: ret
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%a = load <8 x i8>, <8 x i8>* %x
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%b = and i16 %y, 255
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%c = insertelement <8 x i16> poison, i16 %b, i32 0
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%d = shufflevector <8 x i16> %c, <8 x i16> poison, <8 x i32> zeroinitializer
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%e = sext <8 x i8> %a to <8 x i16>
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%f = mul <8 x i16> %d, %e
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ret <8 x i16> %f
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}
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define <8 x i16> @vwmulsu_vx_v8i16_i8_and1(<8 x i8>* %x, i16 %y) {
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; CHECK-LABEL: vwmulsu_vx_v8i16_i8_and1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vle8.v v9, (a0)
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; CHECK-NEXT: andi a0, a1, 254
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; CHECK-NEXT: vwmulsu.vx v8, v9, a0
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; CHECK-NEXT: ret
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%a = load <8 x i8>, <8 x i8>* %x
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%b = and i16 %y, 254
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%c = insertelement <8 x i16> poison, i16 %b, i32 0
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%d = shufflevector <8 x i16> %c, <8 x i16> poison, <8 x i32> zeroinitializer
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%e = sext <8 x i8> %a to <8 x i16>
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%f = mul <8 x i16> %d, %e
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ret <8 x i16> %f
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}
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define <4 x i32> @vwmulsu_vx_v4i32_i16_and(<4 x i16>* %x, i32 %y) {
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; CHECK-LABEL: vwmulsu_vx_v4i32_i16_and:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
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; CHECK-NEXT: vle16.v v9, (a0)
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; CHECK-NEXT: vwmulsu.vx v8, v9, a1
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; CHECK-NEXT: ret
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%a = load <4 x i16>, <4 x i16>* %x
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%b = and i32 %y, 65535
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%c = insertelement <4 x i32> poison, i32 %b, i32 0
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%d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> zeroinitializer
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%e = sext <4 x i16> %a to <4 x i32>
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%f = mul <4 x i32> %d, %e
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ret <4 x i32> %f
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}
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define <4 x i32> @vwmulsu_vx_v4i32_i16_zext(<4 x i16>* %x, i16 %y) {
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; CHECK-LABEL: vwmulsu_vx_v4i32_i16_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
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; CHECK-NEXT: vle16.v v9, (a0)
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; CHECK-NEXT: vwmulsu.vx v8, v9, a1
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; CHECK-NEXT: ret
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%a = load <4 x i16>, <4 x i16>* %x
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%b = zext i16 %y to i32
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%c = insertelement <4 x i32> poison, i32 %b, i32 0
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%d = shufflevector <4 x i32> %c, <4 x i32> poison, <4 x i32> zeroinitializer
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%e = sext <4 x i16> %a to <4 x i32>
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%f = mul <4 x i32> %d, %e
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ret <4 x i32> %f
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}
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