forked from OSchip/llvm-project
[AMDGPU] gfx1010 disassembler changes for wave32
Differential Revision: https://reviews.llvm.org/D63506 llvm-svn: 363721
This commit is contained in:
parent
7ae267dc0f
commit
ab4f2ea793
|
@ -1039,6 +1039,8 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
|
||||||
STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
|
STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
|
||||||
"SDWAVopcDst should be present only on GFX9+");
|
"SDWAVopcDst should be present only on GFX9+");
|
||||||
|
|
||||||
|
bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
|
||||||
|
|
||||||
if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
|
if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
|
||||||
Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
|
Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
|
||||||
|
|
||||||
|
@ -1046,15 +1048,21 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
|
||||||
if (TTmpIdx >= 0) {
|
if (TTmpIdx >= 0) {
|
||||||
return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
|
return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
|
||||||
} else if (Val > SGPR_MAX) {
|
} else if (Val > SGPR_MAX) {
|
||||||
return decodeSpecialReg64(Val);
|
return IsWave64 ? decodeSpecialReg64(Val)
|
||||||
|
: decodeSpecialReg32(Val);
|
||||||
} else {
|
} else {
|
||||||
return createSRegOperand(getSgprClassId(OPW64), Val);
|
return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
return createRegOperand(AMDGPU::VCC);
|
return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
|
||||||
|
return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
|
||||||
|
decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
|
||||||
|
}
|
||||||
|
|
||||||
bool AMDGPUDisassembler::isVI() const {
|
bool AMDGPUDisassembler::isVI() const {
|
||||||
return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
|
return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
|
||||||
}
|
}
|
||||||
|
|
|
@ -123,6 +123,8 @@ public:
|
||||||
MCOperand decodeSDWASrc32(unsigned Val) const;
|
MCOperand decodeSDWASrc32(unsigned Val) const;
|
||||||
MCOperand decodeSDWAVopcDst(unsigned Val) const;
|
MCOperand decodeSDWAVopcDst(unsigned Val) const;
|
||||||
|
|
||||||
|
MCOperand decodeBoolReg(unsigned Val) const;
|
||||||
|
|
||||||
int getTTmpIdx(unsigned Val) const;
|
int getTTmpIdx(unsigned Val) const;
|
||||||
|
|
||||||
bool isVI() const;
|
bool isVI() const;
|
||||||
|
|
Loading…
Reference in New Issue