forked from OSchip/llvm-project
[PowerPC] Add support for intrinsic llvm.ppc.eieio
Add support for the intrinsic llvm.ppc.eieio to emit the instruction eieio. Differential Revision: https://reviews.llvm.org/D69066
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@ -35,6 +35,8 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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def int_ppc_sync : Intrinsic<[], [], []>;
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// lwsync is sync 1
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def int_ppc_lwsync : Intrinsic<[], [], []>;
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// eieio instruction
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def int_ppc_eieio : Intrinsic<[],[],[]>;
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// Intrinsics used to generate ctr-based loops. These should only be
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// generated by the PowerPC backend!
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@ -2325,10 +2325,15 @@ let isCodeGenOnly = 1 in {
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}
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}
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// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
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def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
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"eieio", IIC_LdStLoad, []>;
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def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
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def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
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def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
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def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
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def : Pat<(int_ppc_eieio), (EnforceIEIO)>;
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//===----------------------------------------------------------------------===//
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// PPC32 Arithmetic Instructions.
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@ -4176,10 +4181,6 @@ def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
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def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
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"icbi $src", IIC_LdStICBI, []>;
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// We used to have EIEIO as value but E[0-9A-Z] is a reserved name
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def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
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"eieio", IIC_LdStLoad, []>;
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def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
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"wait $L", IIC_LdStLoad, []>;
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@ -0,0 +1,15 @@
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr | FileCheck %s
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define void @eieio_test() {
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; CHECK-LABEL: @eieio_test
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; CHECK: eieio
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; CHECK-NEXT: blr
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entry:
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tail call void @llvm.ppc.eieio()
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ret void
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}
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declare void @llvm.ppc.eieio()
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