diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 1a42b2358326..b04c6b112682 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1705,6 +1705,9 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
 
     setOperationAction(ISD::UDIV, MVT::i32, Expand);
     setLibcallName(RTLIB::UDIV_I32, ".udiv");
+
+    setLibcallName(RTLIB::SREM_I32, ".rem");
+    setLibcallName(RTLIB::UREM_I32, ".urem");
   }
 
   if (Subtarget->is64Bit()) {
diff --git a/llvm/test/CodeGen/SPARC/soft-mul-div.ll b/llvm/test/CodeGen/SPARC/soft-mul-div.ll
index 7c453dd35be7..a5a7583b930f 100644
--- a/llvm/test/CodeGen/SPARC/soft-mul-div.ll
+++ b/llvm/test/CodeGen/SPARC/soft-mul-div.ll
@@ -63,3 +63,44 @@ define i8 @test_udiv8(i8 %a, i8 %b) #0 {
     ret i8 %d
 }
 
+define i32 @test_srem32(i32 %a, i32 %b) #0 {
+    ; CHECK-LABEL: test_srem32
+    ; CHECK:       call .rem
+    %d = srem i32 %a, %b
+    ret i32 %d
+}
+
+define i16 @test_srem16(i16 %a, i16 %b) #0 {
+    ; CHECK-LABEL: test_srem16
+    ; CHECK:       call .rem
+    %d = srem i16 %a, %b
+    ret i16 %d
+}
+
+define i8 @test_srem8(i8 %a, i8 %b) #0 {
+    ; CHECK-LABEL: test_srem8
+    ; CHECK:       call .rem
+    %d = srem i8 %a, %b
+    ret i8 %d
+}
+
+define i32 @test_urem32(i32 %a, i32 %b) #0 {
+    ; CHECK-LABEL: test_urem32
+    ; CHECK:       call .urem
+    %d = urem i32 %a, %b
+    ret i32 %d
+}
+
+define i16 @test_urem16(i16 %a, i16 %b) #0 {
+    ; CHECK-LABEL: test_urem16
+    ; CHECK:       call .urem
+    %d = urem i16 %a, %b
+    ret i16 %d
+}
+
+define i8 @test_urem8(i8 %a, i8 %b) #0 {
+    ; CHECK-LABEL: test_urem8
+    ; CHECK:       call .urem
+    %d = urem i8 %a, %b
+    ret i8 %d
+}