forked from OSchip/llvm-project
[Hexagon] Minor cleanups in isel lowering
llvm-svn: 334015
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@ -1356,22 +1356,21 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
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setOperationAction(ISD::BSWAP, MVT::i32, Legal);
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setOperationAction(ISD::BSWAP, MVT::i64, Legal);
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setOperationAction(ISD::MUL, MVT::i64, Legal);
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for (unsigned IntExpOp :
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{ ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
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ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
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ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
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ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
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setOperationAction(IntExpOp, MVT::i32, Expand);
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setOperationAction(IntExpOp, MVT::i64, Expand);
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{ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
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ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
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ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
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ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
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for (MVT VT : MVT::integer_valuetypes())
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setOperationAction(IntExpOp, VT, Expand);
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}
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for (unsigned FPExpOp :
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{ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
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ISD::FPOW, ISD::FCOPYSIGN}) {
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setOperationAction(FPExpOp, MVT::f32, Expand);
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setOperationAction(FPExpOp, MVT::f64, Expand);
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for (MVT VT : MVT::fp_valuetypes())
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setOperationAction(FPExpOp, VT, Expand);
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}
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// No extending loads from i32.
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