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During two-address lowering, rescheduling an instruction does not untie 

operands. Make TryInstructionTransform return false to reflect this.
Fixes PR11861.

llvm-svn: 153892
This commit is contained in:
Lang Hames 2012-04-02 19:58:43 +00:00
parent d6fbc8ff66
commit aaafacd07e
2 changed files with 26 additions and 2 deletions
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4
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1248,7 +1248,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
// re-schedule this MI below it.
if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
++NumReSchedDowns;
return true;
return false;
}
if (TargetRegisterInfo::isVirtualRegister(regA))
@ -1270,7 +1270,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
// re-schedule it before this MI if it's legal.
if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
++NumReSchedUps;
return true;
return false;
}
// If this is an instruction with a load folded into it, try unfolding

24
llvm/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llc < %s
; PR11861
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi"
define arm_aapcs_vfpcc void @foo() nounwind align 2 {
br i1 undef, label %5, label %1
; <label>:1 ; preds = %0
%2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%3 = bitcast <2 x i64> %2 to <4 x float>
store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0
store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0
store <4 x float> %3, <4 x float>* undef, align 16, !tbaa !0
%4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2
store <4 x float> %4, <4 x float>* undef, align 16, !tbaa !0
unreachable
; <label>:5 ; preds = %0
ret void
}
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}